A serial IGBT voltage equalization method and system based on an auxiliary voltage source is disclosed. The method includes the following steps. (1) Detect a port dynamic voltage of each serial IGBT. (2) Perform dynamic overvoltage diagnosis respectively on the port dynamic voltage of each IGBT. (3) Supply emergency high level signal to the gate of the IGBT when there is dynamic overvoltage. (4) Stop supplying emergency high level signal to the gate of the IGBT, supply a constant voltage at the gate of the IGBT through the auxiliary voltage source. The invention provides a constant voltage through the auxiliary voltage source, prolongs the off time of the faulty IGBT, and turns off other IGBTs simultaneously, thereby achieving the purpose of serial IGBT voltage equalization.

Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper-main lead of the transistor, through the transistor, and from a lower-main lead of the transistor to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower-main lead to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower-control lead the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

The disclosure relates to solid state relay circuit for switching an electrical load. The solid state relay circuit may include a relay transistor; and a driver circuit comprising a constant current source. The driver circuit is configured and arranged to switchably operate the relay transistor, and the relay transistor is configured and arranged to switchably operate the electrical load.

A method for avoiding parasitic oscillation in a parallel semiconductor switch includes allowing only one of the plurality of power components to control a turn-on transition of the semiconductor switch and allowing only one of the plurality of power components to control a turn-off transition of the semiconductor switch, by setting unbalanced driving impedances for the plurality of power components coupled in parallel. Parasitic oscillation in a switch transition may be avoided without impedance matching, and the switch transition may provide a relatively small impact on switch characteristics.

A protective circuit for a semiconductor switch includes a clamp diode, an NPN bipolar transistor, a PNP bipolar transistor, a capacitor connected in parallel with the base-emitter path of the PNP bipolar transistor, and at least three resistors. The bipolar transistors are connected to a thyristor structure that is connected to the cathode of the clamp diode. A first resistor is connected in parallel with the base-emitter path of the NPN bipolar transistor. A first terminal of the second resistor is connected to the base of the PNP bipolar transistor. Either a third resistor is connected in parallel with the base-emitter path of the PNP bipolar transistor, or a first terminal of the third resistor is connected to the emitter of the PNP bipolar transistor and the second terminal of the third resistor is connected to the second terminal of the second resistor.

A gate drive circuit includes one output element, a constant current drive circuit, and a constant voltage drive circuit. The output element outputs a gate drive signal to a gate of a gate driven switching element. The constant current drive circuit causes the output element to output the gate drive signal with a constant current. The constant voltage drive circuit causes the output element to output the gate drive signal with a constant voltage.

Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET and thereby commutating a first shutoff current through a lower base of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

A protection circuit for a semiconductor switch has a gate that can be controlled by a gate driver. The protection circuit includes an integrator for detecting a gate charge of the gate and a comparator unit for switching off the semiconductor switch in dependence on the value of the gate charge relative to a reference charge.

A semiconductor device having a semiconductor chip and a control circuit. The semiconductor chip has a gate electrode pad connected to the gate of an output element and the gate of a current monitor element, a sense emitter electrode pad connected to the sense emitter of the current monitor element and to the anode of the temperature detection diode via a current limiting element, and a cathode electrode pad that is connected to the cathode of the temperature detection diode, the cathode being grounded without being connected to the emitter of the output element. In a temperature detection mode, the control circuit receives a temperature detection voltage via the sense emitter electrode pad and detects the temperature state of the output element. In a current detection mode, the control circuit receives a sense current via the sense emitter electrode pad and detects the current state of the output element.

Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper collector-emitter of the transistor, through the transistor, and from a lower collector-emitter to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower collector-emitter to the lower terminal by opening a lower-main FET and thereby commutating a first shutoff current through a lower base of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.