A reverse current suppression circuit for a PMOS transistor, which includes: a gate drive unit, when the source potential of the first PMOS transistor is lower than the drain potential, the gate drive unit making the gate potential of the first PMOS transistor equal to the drain potential, so that the first PMOS transistor comes into a reverse current suppression state; and a substrate switching unit, when the source potential of the first PMOS transistor is lower than the drain potential, the substrate switching unit short-circuiting the substrate of the first PMOS transistor with the drain of the first PMOS transistor. According to the present invention, when the source potential of the PMOS transistor is lower than the drain potential, the PMOS transistor can be controlled to operate in the reverse current suppression state, so that the PMOS transistor can be effectively protected.

A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.

Disclosed herein is an overcurrent protection circuit configured to, upon detection of an output current that flows through a switch element reaching a first overcurrent limit value, reduce an overcurrent limit value for the output current from the first overcurrent limit value to a second overcurrent limit value smaller than the first overcurrent limit value.

A shoot-through protection circuit includes a current sensor providing a sensor signal connected to a comparator input via at least a burden resistor. A switch protection circuit including a protection input connected to an output of the comparator and a plurality of outputs. Each of the outputs is connected to a corresponding switch in a plurality of stacked switches. Wherein the switch protection circuit is configured to drive each switch of the plurality of stacked switches open in response to a positive output signal from the comparator.

A semiconductor integrated circuit device includes a control unit configured to control a switching element or an output transistor of a power supply device, a monitor terminal for monitoring an output voltage of the power supply device, a test unit configured to output a test signal to the monitor terminal before activation of the power supply device, and a determination unit configured to determine whether or not the monitor terminal is open, on the basis of a voltage of the monitor terminal when the test unit outputs the test signal to the monitor terminal.

Circuitry for reducing the energy losses of a snubber circuit used to protect current switching devices from overvoltage, comprising a switching cell consisting of a switch with alternating opposite conduction states, the switch being serially connected via one contact to a first diode, the switch includes an inherent output capacitance, the switch connects, via a first stray inductance), between one port of a power supply and an output inductor feeding a load, and the first diode connects, via a second stray inductance, between the other port of the power supply and the output inductor, such that whenever the switch passes from a conducting state to a non-conducting state, its inherent output capacitance is charged by a current pulse from the first stray inductance; a snubber circuit consisting of a ferrite bead, a snubber capacitor and a second diode, the snubber circuit being connecting between the other contact of the switch and the other port, for discharging at least a portion of the charge across the inherent output capacitance of the switch to the snubber capacitor via the other port.

A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

In described examples, a first transistor has: a drain coupled to a source of a depletion-mode transistor; a source coupled to a first voltage node; and a gate coupled to a control node. A second transistor has: a drain coupled to a gate of the depletion-mode transistor; a source coupled to the first voltage node; and a gate coupled through at least one first logic device to an input node. A third transistor has: a drain coupled to the gate of the depletion-mode transistor; a source coupled to a second voltage node; and a gate coupled through at least one second logic device to the input node.

A power converter includes a semiconductor element disposed on a substrate, a thermistor element for detecting the temperature of the substrate, the thermistor element being disposed on the substrate, a current detection resistor having one end connected to a ground side node and another end that is grounded, a first voltage detection unit configured to detect a first potential at the other end of the current detection resistor and a second potential at the ground side node, and output a first detection signal, a control unit configured to control the semiconductor element based on the first detection signal, a temperature detection resistor having one end that is connected to a reference potential and another end that is connected to a detection node, and a temperature detection unit configured to detect a temperature based on a third potential at the detection node, and output a temperature information signal.