According to one embodiment, a semiconductor device includes first, and second conductive members, a first electrode including first and second electrode regions, a second electrode electrically connected to a first semiconductor film portion, a first semiconductor region including first to fourth partial regions, a second semiconductor region including the first semiconductor film portion, a third semiconductor region including a first semiconductor layer portion, a fourth semiconductor region provided between the first electrode and the first semiconductor region, and a first insulating member including insulating portions. The first partial region is between the first electrode region and the first conductive member. The second partial region is between the second electrode region and the second conductive member. The third partial region is between the first and second partial regions and between the first electrode and the fourth partial region. The fourth partial region is between the first and second conductive members.

According to one embodiment, a semiconductor device includes first, and second conductive members, a first electrode including first and second electrode regions, a second electrode electrically connected to a first semiconductor film portion, a first semiconductor region including first to fourth partial regions, a second semiconductor region including the first semiconductor film portion, a third semiconductor region including a first semiconductor layer portion, a fourth semiconductor region provided between the first electrode and the first semiconductor region, and a first insulating member including insulating portions. The first partial region is between the first electrode region and the first conductive member. The second partial region is between the second electrode region and the second conductive member. The third partial region is between the first and second partial regions and between the first electrode and the fourth partial region. The fourth partial region is between the first and second conductive members.

A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

There is disclosed a Connected Synthetic Physically Unclonable Function (acronym CSPUF) made of a circuit configured to receive signals of one or more sensors and/or actuators in/of a computer device; determine one or more statistical properties of the noise distribution of the selected one or more of the sensors and/or actuators; receive data IN from one or more external data sources; determine one or more digital signatures (responses) from the statistical properties and the selected external data. In one embodiment, along a response R when challenged by a challenge C, the circuit is configured to receive data IN and/or to communicate data OUT from one or more external data sources. Developments describe uses and advantages of data IN and data OUT channels, e.g. static or dynamic calibration, options to disable the circuit. Other embodiments consider variants of interconnections of two CSPUF circuits, providing “self-cycled”, “iterative”, “cascaded” and other “blockchain” arrangements.

In certain embodiments, driver circuitry generates drive signals to drive driven circuitry to transition between first and second states. The driver circuitry has a first-to-second driver circuit that generates a first drive signal to drive the driven circuitry to transition from the first state to the second state and a second-to-first driver circuit that generates a second drive signal to drive the driven circuitry to transition from the second state to the first state. The driver circuitry includes two complementary triggered current pulse generators (described in U.S. Pat. No. 10,554,206) that combine to efficiently provide switch drive for a FET or other reactive load. The triggered drive has fast edges for low switching losses. In certain embodiments, the low power triggered drive circuitry can respond to a slowly changing feedback signal to switch a FET so as to regulate a power converter output.

A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

An n-type transistor and a p-type transistor are connected in series such that, when the two transistors are turned on, current flows from the collector of the n-type transistor to the collector of the p-type transistor. A positive-feedback capacitor is connected between the collector of one transistor and the base of the other transistor. The two transistors turn on together when the base voltage of the n-type transistor exceeds the base voltage of the p-type transistor by at least the sum of the turn-on threshold voltages of the two transistors and (i) the two transistors turn off together when the base voltage of the n-type transistor fails to exceed the base voltage of the p-type transistor by at least that sum. The positive-feedback capacitor ensures that the two transistors turn fully on and off together. In certain embodiments, the circuitry can be controlled to operate as a current pulse generator.

In certain embodiments, driver circuitry generates drive signals to drive driven circuitry to transition between first and second states. The driver circuitry has a first-to-second driver circuit that generates a first drive signal to drive the driven circuitry to transition from the first state to the second state and a second-to-first driver circuit that generates a second drive signal to drive the driven circuitry to transition from the second state to the first state. The driver circuitry includes two complementary triggered current pulse generators (described in U.S. Pat. No. 10,554,206) that combine to efficiently provide switch drive for a FET or other reactive load. The triggered drive has fast edges for low switching losses. In certain embodiments, the low power triggered drive circuitry can respond to a slowly changing feedback signal to switch a FET so as to regulate a power converter output.

An n-type transistor and a p-type transistor are connected in series such that, when the two transistors are turned on, current flows from the collector of the n-type transistor to the collector of the p-type transistor. A positive-feedback capacitor is connected between the collector of one transistor and the base of the other transistor. The two transistors turn on together when the base voltage of the n-type transistor exceeds the base voltage of the p-type transistor by at least the sum of the turn-on threshold voltages of the two transistors and (i) the two transistors turn off together when the base voltage of the n-type transistor fails to exceed the base voltage of the p-type transistor by at least that sum. The positive-feedback capacitor ensures that the two transistors turn fully on and off together. In certain embodiments, the circuitry can be controlled to operate as a current pulse generator.

An n-type transistor and a p-type transistor are connected in series such that, when the two transistors are turned on, current flows from the collector of the n-type transistor to the collector of the p-type transistor. A positive-feedback capacitor is connected between the collector of one transistor and the base of the other transistor. The two transistors turn on together when the base voltage of the n-type transistor exceeds the base voltage of the p-type transistor by at least the sum of the turn-on threshold voltages of the two transistors and (i) the two transistors turn off together when the base voltage of the n-type transistor fails to exceed the base voltage of the p-type transistor by at least that sum. The positive-feedback capacitor ensures that the two transistors turn fully on and off together. In certain embodiments, the circuitry can be controlled to operate as a current pulse generator.