An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

An n-type transistor and a p-type transistor are connected in series such that, when the two transistors are turned on, current flows from the collector of the n-type transistor to the collector of the p-type transistor. A positive-feedback capacitor is connected between the collector of one transistor and the base of the other transistor. The two transistors turn on together when the base voltage of the n-type transistor exceeds the base voltage of the p-type transistor by at least the sum of the turn-on threshold voltages of the two transistors and (i) the two transistors turn off together when the base voltage of the n-type transistor fails to exceed the base voltage of the p-type transistor by at least that sum. The positive-feedback capacitor ensures that the two transistors turn fully on and off together. In certain embodiments, the circuitry can be controlled to operate as a current pulse generator.

Disclosed is a variable coding method for realizing chip reuse, comprising the following steps: using at least two identical integrated circuit chips, wherein each integrated circuit chip executes different control logic truth tables according to different gating signals; introducing at least one logical control signal as a gating signal; and controlling the logical control signal, so that each integrated circuit chip respectively executes a corresponding control logic truth table. Also disclosed is a communication terminal using the variable coding method for realizing chip reuse. Two or more completely identical integrated circuit chips can be used to realize different logical control functions, thereby simplifying the type of a chip for realizing a system function, and greatly reducing the development costs of an integrated circuit system and the management complexity of a mass production supply chain.

The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.

An electrostatic protection circuit is disclosed. The electrostatic protection circuit includes delay circuitry coupled between a supply voltage node and a fixed voltage node. The electrostatic protection circuit also includes latch circuitry made up of current-limiting circuitry that includes a gallium arsenide transistor and a latch. The current-limiting circuitry and the latch are coupled between the supply voltage node and the fixed voltage node, and the current-limiting circuitry is also coupled to the delay circuitry. The electrostatic protection circuit further includes discharge circuitry coupled between the supply voltage node and the fixed voltage node and to the latch, wherein the latch is configured to drive the discharge circuitry to short the supply voltage node to the fixed voltage node during an electrostatic discharge event, and the current-limiting circuitry is configured to limit latch current from the supply voltage node to the latch during normal operation.

An electrostatic protection circuit is disclosed. The electrostatic protection circuit includes delay circuitry coupled between a supply voltage node and a fixed voltage node. The electrostatic protection circuit also includes latch circuitry made up of current-limiting circuitry that includes a gallium arsenide transistor and a latch. The current-limiting circuitry and the latch are coupled between the supply voltage node and the fixed voltage node, and the current-limiting circuitry is also coupled to the delay circuitry. The electrostatic protection circuit further includes discharge circuitry coupled between the supply voltage node and the fixed voltage node and to the latch, wherein the latch is configured to drive the discharge circuitry to short the supply voltage node to the fixed voltage node during an electrostatic discharge event, and the current-limiting circuitry is configured to limit latch current from the supply voltage node to the latch during normal operation.

A method and apparatus for forcing equivalent outputs at start-up for replicated sequential circuits is disclosed. An integrated circuit (IC) includes first and second clocked logic circuits each coupled to receive a clock signal common to both, and each configured to produce equivalent logical outputs based on a common set of logic inputs. The IC further includes an equivalence circuit coupled to the outputs of each of the first and second clocked logic circuits. During a system start-up (e.g., power on) and before the clock signal has been applied, the equivalence circuit may detect if the outputs of the to first and second clocked logic circuits originally come up in different states. Responsive to determining that the outputs of the first and second clocked logic circuits are different, the equivalence circuit may cause the outputs to be forced to the same logical state.

An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

Disclosed is a variable coding method for realizing chip reuse, comprising the following steps: using at least two identical integrated circuit chips, wherein each integrated circuit chip executes different control logic truth tables according to different gating signals; introducing at least one logical control signal as a gating signal; and controlling the logical control signal, so that each integrated circuit chip respectively executes a corresponding control logic truth table. Also disclosed is a communication terminal using the variable coding method for realizing chip reuse. Two or more completely identical integrated circuit chips can be used to realize different logical control functions, thereby simplifying the type of a chip for realizing a system function, and greatly reducing the development costs of an integrated circuit system and the management complexity of a mass production supply chain.

A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.