H03K19/091

Layout-friendly test pattern decompressor

A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Layout-friendly test pattern decompressor

A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Layout-Friendly Test Pattern Decompressor

A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Performance-on-demand IC chip design in integrated-injection logic

A circuit comprising a first injection BJT in a common-base configuration and configured to output a first injection current at its collector. A first multiple-collector BJT is in an open collector configuration, is electrically coupled to the first injection BJT, and is arranged to receive the first injection current at its base. The first multiple-collector BJT has a capacitance load at one of its collectors. A first supply voltage is electrically coupled to the first injection BJT. The first supply voltage is configured to dynamically adjust during operation of the circuit in response to a change in the capacitance load of the first multiple-collector BJT.