An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.

According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output. This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs. The logic type offers higher operation speed compared to the existing solutions.

The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

A semiconductor device includes first, second and third semiconductor regions, each surrounded by an element isolation layer, first and second transistors of the first semiconductor region connected in parallel between first and second nodes, a third transistor of the second semiconductor region between the second node and the first transistor, and a fourth transistor of the third semiconductor region between the second node and the second transistor. Gates of the first and second transistors extend in a first direction and are spaced from each other in a second direction. A first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction.

A semiconductor device includes first, second and third semiconductor regions, each surrounded by an element isolation layer, first and second transistors of the first semiconductor region connected in parallel between first and second nodes, a third transistor of the second semiconductor region between the second node and the first transistor, and a fourth transistor of the third semiconductor region between the second node and the second transistor. Gates of the first and second transistors extend in a first direction and are spaced from each other in a second direction. A first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction.

The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.

The disclosed driver and memory include: a phase driver that receives a first voltage signal, configured to output a second phase signal according to the first phase signal and the first voltage signal; a complementary phase driver includes: a first inverter for generating a complementary inverted phase signal based on a first complementary phase signal, the first phase signal and the first complementary phase signal are mutually inverted; a second inverter for receiving an output signal of the first inverter and a second voltage signal, the voltage value of the second voltage signal is smaller than that of the first voltage signal, and the second inverter is configured to be based on the first complementary inverted phase signal, and the second voltage signal outputs a second complementary phase signal. The driver of the embodiment provides the second phase signal and the second complementary phase signal.

A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor.

An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.

According to the invention, only one type of enhancement MOS transistor type is used in implementing typical Boolean functions in hardware. Preferably, the MOS transistor type allows back bias control for adjusting and compensating the operation conditions. When implemented in PMOS only transistors, the pull-down functionality is performed by a single transistor with its gate and source connected to the output, This type of connection ensures that the pull-down functionality is performed by the leakage current of the pull-down transistor. The leakage currents of all the pull-up transistors need to be smaller than this pull-down current when all the pull-up paths are off. The ratio of these off-currents can be adjusted by the aspect ratios of the transistors. The logic type offers extremely low current consumption with low voltages and offers the possibility to avoid more complex shut-down circuitry often used in ultra low-power designs. The logic type offers higher operation speed compared to the existing solutions.