The present disclosure describes a power supply switch that includes a voltage generator, a switch circuit, and a confirmation circuit. The voltage generator is configured to compare a first power supply voltage to a second power supply voltage and to output the first power supply voltage or the second power supply voltage as a bulk voltage (V.sub.bulk). The switch circuit includes one or more transistors and is configured to (i) bias bulk terminals of the one or more transistors with the V.sub.bulk and (ii) output either the first power supply voltage or the second power supply voltage as a voltage output signal. The confirmation circuit is configured to output a confirmation signal that indicates whether the voltage output signal transitioned from the first power supply voltage to the second power supply voltage.

Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.

A signal processing device according to the present technology includes a multistage-branching-wired-line unit that supplies the same signal to a plurality of target elements via multistage-branched wired lines, and a logic circuit arranged at each of stages of the multistage-branching-wired-line unit, in which the wired lines in at least a certain space between the stages in the multistage-branching-wired-line unit cross each other.

An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

A logic process-based level conversion circuit of a flash flash field programmable gate array (FPGA) performs three-stage level conversion by using three conversion modules. A first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain, an intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain, and a drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a drive word line. The logic process-based level conversion circuit reduces the pressure of conversion at each stage, ensures a capability of driving the next stage, increases the conversion speed, and provides a large driving capability at the last stage.

A high-voltage power supply system including a high-voltage regulator, a function generator, and a triggering circuit. The high-voltage regulator includes a microcontroller, a digital-to-analog convertor in communication with the microcontroller, and a high-voltage DC-DC converter in communication with the digital-to-analog converter. The function generator includes a high-voltage inverter including one or more MOSFET switches. The high-voltage inverter is in communication with the microcontroller of the high-voltage regulator. The triggering circuit includes one or more high-voltage electromechanical switches.

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.

A communications system includes: a control device; a standard proxy input/output circuit configured to control a standard electric device; and an extension proxy input/output circuit configured to control an extension electric device. The control device and the standard proxy input/output circuit are provided on one substrate, and the control device and the extension proxy input/output circuit are connected to each other via an electric wire.

An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.