A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.

A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

The present disclosure describes techniques for incorporating pipelined DSP blocks or other types of embedded functions into a logic circuit with a slower clock rate without any clock crossing complexities, and at the same time managing the power consumption of the more complex design that results from it. The techniques include generating a faster clock or several faster clocks that may have a faster clock rate than the clock used by the logic circuit and that may be used as clock input to the embedded pipelined DSP blocks. In addition, the present disclosure describes techniques for generating, improving, and using the faster clock to sample the output of a logic circuit using pulses of generated faster clock, which may allow to increase the clock frequency of the circuit to an optimal level, while maintaining functional correctness.

A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where the first input end is configured to receive high level signal, the second input end is configured to receive low level signal, the control ends are connected to selection unit and the output end is connected to a serial wire, and the selection unit is configured to receive selection signal and at least two branch signals, and is configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch; the serial wire, configured to organize signals output by the parallel branches into a serial signal; and a drive unit, connected to the serial wire for enhancing drive capability of the serial wire, where an output end of the drive unit is configured to output the serial signal.

Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and/or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and/or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.

A control circuit including a quadrature encoder circuit, a counter circuit, and a cutoff circuit is provided. The quadrature encoder circuit generates a first edge signal and a first direction signal according to a first external signal and a second external signal. The counter circuit performs a counting operation according to the first edge signal and the first direction signal. In response to the timer signal being enabled, the cutoff circuit prevents the first edge signal and the first direction signal from entering the counter circuit and provides a second edge signal and a second direction signal to the counter circuit so that the counter circuit performs the counting operation according to the second edge signal and the second direction signal.