Provided are a method of dynamically configuring a FPGA and a network security device. The network security device includes a CPU and at least one FPGA coupled with the CPU. The CPU generates a configuration entry for a target FPGA in response to a user instruction. The configuration entry includes a classification number and a configuration content for the target FPGA. The CPU sends the configuration entry to each FPGA coupled with the CPU, Each FPGA obtains its own classification number, compares its own classification number with the classification number in the configuration entry, and stores the configuration content when the own classification number the same with the classification number in the configuration entry.

Provided are a method of dynamically configuring a FPGA and a network security device. The network security device includes a CPU and at least one FPGA coupled with the CPU. The CPU generates a configuration entry for a target FPGA in response to a user instruction. The configuration entry includes a classification number and a configuration content for the target FPGA. The CPU sends the configuration entry to each FPGA coupled with the CPU, Each FPGA obtains its own classification number, compares its own classification number with the classification number in the configuration entry, and stores the configuration content when the own classification number the same with the classification number in the configuration entry.

Provided are a reconfigurable processor and a method of operating the same, the reconfigurable processor including: a configurable memory configured to receive a task execution instruction from a control processor; and a plurality of reconfigurable arrays, each configured to receive configuration information from the configurable memory, wherein each of the plurality of reconfigurable arrays simultaneously executes a task based on the configuration information.

Reconfigurable Integrated Circuit with On-Chip Configuration Generation A circuit and method are provided in which reconfiguration is achieved through the modification of a dynamic data path using configuration information generated on the basis of run-time variables. Rather than storing a plurality of pre-set configurations, this can allow configurations optimised to processing tasks to be implemented during operation.

A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic. At least four logic elements may be interconnected with diagonal direct links.

A system and method for processing queries including splitting a query into sub-queries, mapping the sub-queries to respective sets of filter properties, mapping the sets of filter properties to respective reconfiguration bitstreams, configuring a plurality of filters within a field programmable gate array (FPGA) according to respective ones of the respective reconfiguration bitstreams, wherein each filter is formed in a respective reconfigurable region of the FPGA.

A system and method for processing queries including splitting a query into sub-queries, mapping the sub-queries to respective sets of filter properties, mapping the sets of filter properties to respective reconfiguration bitstreams, configuring a plurality of filters within a field programmable gate array (FPGA) according to respective ones of the respective reconfiguration bitstreams, wherein each filter is formed in a respective reconfigurable region of the FPGA.

A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.

A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.

A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.