A power chip with a switching converter, having: a power pin configured to receive an input voltage, an indicating signal generating circuit configured to generate an indicating signal; a communicating circuit configured to receive/transmit communication data; and a multi-function pin configured to receive/transmit communication data and/or to provide the indicating signal under certain conditions.

A power chip with a switching converter, having: a power pin configured to receive an input voltage, an indicating signal generating circuit configured to generate an indicating signal; a communicating circuit configured to receive/transmit communication data; and a multi-function pin configured to receive/transmit communication data and/or to provide the indicating signal under certain conditions.

An electronic device has a power rail that is driven by voltage regulators and provides a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and voltage regulator controller and operates in a standby mode or an operational mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not deliver current to the power rail, while in the operational mode, the bypass unit does not bypass the feedback path and the respective voltage regulator delivers up to the predefined regulator current to the power rail.

An electronic device has a power rail that is driven by voltage regulators and provides a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and voltage regulator controller and operates in a standby mode or an operational mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not deliver current to the power rail, while in the operational mode, the bypass unit does not bypass the feedback path and the respective voltage regulator delivers up to the predefined regulator current to the power rail.

An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

A data retention circuit is provided in the invention. The data retention circuit includes a master latch circuit, a slave latch circuit, and a control circuit. The control circuit is coupled to the master latch circuit and the slave latch circuit and receives a clock signal from a clock circuit and a power management signal from a power management unit (PMU). In a normal operation mode, the control circuit transmits the clock signal to the master latch circuit and the slave latch circuit. In sleep mode, power to the master latch circuit is switched off and the control circuit transmits the power management signal to the slave latch circuit.

This disclosure relates generally to data processing, and more particularly, to methods and systems for memory initialization of an integrated circuit. In one embodiment, a method for memory initialization at a circuitry is provided. The method comprises: identifying a portion of the circuitry configured as a memory device; detecting a start of a power-off state for a power domain within the circuitry including the memory device; performing a write operation to write data of a pre-determined pattern to the memory device upon detecting the start of the power-off state; and providing the data stored at the memory device for a reading operation after the power-off state ends.

An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

The present disclosure relates to a power control device, a driving module and a switching power supply device. The power control device includes: a control terminal, configured to input and output a control signal to and from the driving module; an enable output terminal, configured to output an enable signal to the driving module; a control circuit; and an input/output circuit, configured to have the control signal be a first logic level when the output transistor is turned on and the synchronous rectifier transistor is turned off, and to have the control signal be a second logic level when the output transistor is turned off and the synchronous rectifier transistor is turned on, and to be able to become an input standby state according to an instruction from the control circuit.