A method for providing more than one function to pins of a programmable device used in a server system includes the programmable device and first and second devices. The programmable device is electrically connected to the first device and the second device. The programmable device includes a major logic communication device, a detection module, a storage module, and at least one multiplexing pin. The second device is powered on, sending an in-position signal to the detection module through the at least one multiplexing pin. The detection module transmits the in-position signal to the storage module. The major logic communication module communicates with the first device through the at least one multiplexing pin. A system applying the method are also disclosed.

A method for providing more than one function to pins of a programmable device used in a server system includes the programmable device and first and second devices. The programmable device is electrically connected to the first device and the second device. The programmable device includes a major logic communication device, a detection module, a storage module, and at least one multiplexing pin. The second device is powered on, sending an in-position signal to the detection module through the at least one multiplexing pin. The detection module transmits the in-position signal to the storage module. The major logic communication module communicates with the first device through the at least one multiplexing pin. A system applying the method are also disclosed.

A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

A power supply switch circuit includes a first transistor that switches supplying of a first power supply voltage to a power supply terminal of a power amplifier, a switch controller that controls the first transistor and to which a second power supply voltage is applied, and a voltage selector that selects a higher voltage among the first power supply voltage and the second power supply voltage. The selected higher voltage is applied to a body terminal of the first transistor or a gate terminal of the first transistor.

A power supply switch circuit includes a first transistor that switches supplying of a first power supply voltage to a power supply terminal of a power amplifier, a switch controller that controls the first transistor and to which a second power supply voltage is applied, and a voltage selector that selects a higher voltage among the first power supply voltage and the second power supply voltage. The selected higher voltage is applied to a body terminal of the first transistor or a gate terminal of the first transistor.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

A timer circuit switches a second changeover switch and a third changeover switch to a pulse output unit for a certain period of time when power supply is started, and causes the pulse output unit to output a code pulse to a second communication line. An input-output control unit switches a first changeover switch to a first terminal for the certain period of time when the power supply is started, determines whether a code indicated by the code pulse received from the first terminal is a regular code, and cuts off electric power supplied from a first power supply line to a second power supply line when the code is not the regular code.

A timer circuit switches a second changeover switch and a third changeover switch to a pulse output unit for a certain period of time when power supply is started, and causes the pulse output unit to output a code pulse to a second communication line. An input-output control unit switches a first changeover switch to a first terminal for the certain period of time when the power supply is started, determines whether a code indicated by the code pulse received from the first terminal is a regular code, and cuts off electric power supplied from a first power supply line to a second power supply line when the code is not the regular code.