H03K19/212

Entropy server for random number generation

Embodiments include method, systems and computer program products for providing entropy to generate random numbers.

Performance power optimized full adder

A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.

ENTROPY SERVER FOR RANDOM NUMBER GENERATION

Embodiments include method, systems and computer program products for providing entropy to generate random numbers.

System and method for complimentary VT-drop ambipolar carbon nanotube logic

A logic gate and a cascaded logic family is described that uses the unique ambipolar behavior, e.g., of carbon nanotubes. A complementary VT-drop ambipolar carbon nanotube logic can provide a decrease in device count compared to previous ambipolar carbon nanotube field effect transistor logic structures, enabling power and/or speed improvements.

PERFORMANCE POWER OPTIMIZED FULL ADDER

A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.

Variable coding method for realizing chip reuse and communication terminal therefor
10320385 · 2019-06-11 · ·

Disclosed is a variable coding method for realizing chip reuse, comprising the following steps: using at least two identical integrated circuit chips, wherein each integrated circuit chip executes different control logic truth tables according to different gating signals; introducing at least one logical control signal as a gating signal; and controlling the logical control signal, so that each integrated circuit chip respectively executes a corresponding control logic truth table. Also disclosed is a communication terminal using the variable coding method for realizing chip reuse. Two or more completely identical integrated circuit chips can be used to realize different logical control functions, thereby simplifying the type of a chip for realizing a system function, and greatly reducing the development costs of an integrated circuit system and the management complexity of a mass production supply chain.

SYSTEM AND METHOD FOR COMPLIMENTARY VT-DROP AMBIPOLAR CARBON NANOTUBE LOGIC

A logic gate and a cascaded logic family is described that uses the unique ambipolar behavior, e.g., of carbon nanotubes. A complementary VT-drop ambipolar carbon nanotube logic can provide a decrease in device count compared to previous ambipolar carbon nanotube field effect transistor logic structures, enabling power and/or speed improvements.

VARIABLE CODING METHOD FOR REALIZING CHIP REUSE AND COMMUNICATION TERMINAL THEREFOR
20180351553 · 2018-12-06 ·

Disclosed is a variable coding method for realizing chip reuse, comprising the following steps: using at least two identical integrated circuit chips, wherein each integrated circuit chip executes different control logic truth tables according to different gating signals; introducing at least one logical control signal as a gating signal; and controlling the logical control signal, so that each integrated circuit chip respectively executes a corresponding control logic truth table. Also disclosed is a communication terminal using the variable coding method for realizing chip reuse. Two or more completely identical integrated circuit chips can be used to realize different logical control functions, thereby simplifying the type of a chip for realizing a system function, and greatly reducing the development costs of an integrated circuit system and the management complexity of a mass production supply chain.