This application relates to a synchronization circuit for synchronizing signals used in a threshold implementation operation process performing in an S-box of an encryption circuit. In one aspect, the synchronization circuit includes an enable signal generator configured to generate an enable signal. The synchronization circuit may also include a synchronization unit included in an encryption circuit and located inside an S-box that performs a threshold implementation operation that calculates by dividing bits of an input signal into bits equal to or greater than the number of bits of the input signal. The synchronization unit may be configured to synchronize signals used in a threshold implementation operation process based on the generated enable signal.

A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.

High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.

A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

Embodiments provide a method for data storage and comparison, a storage comparison circuit device, and a semiconductor memory. The storage comparison circuit device includes a latch and a comparator. The latch is configured to latch inputted first input data and output first output data and second output data. The first output data are the same as the first input data, whereas the second output data are different from the first input data, wherein the first output data and the second output data are respectively inputted into the comparator. The comparator is configured to receive second input data, the first output data and the second output data, and to output a comparison result. By using modular structures of the latch and the comparator, device data can be simplified for the latch and the comparator, chip area can be reduced, calculation amount can be reduced, and efficiency of data comparison can be improved.

An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

The disclosure relates to a low-loss arithmetic circuit, which includes a plurality of arithmetic units, a plurality of storage units, and one or more reset MOSFETs. Each arithmetic unit includes 4 MOSFETs. The disclosure also relates to an operating method of the low-loss arithmetic circuit and a low-loss Processing-in-Memory circuit.

Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.