A pulse output device which corrects a pulse signal advanced or delayed from a timing prescribed by a control device and a control system including the pulse output device are provided. A PLC system including a driving device, a CPU unit, and a pulse output unit is provided. The pulse output unit includes a clock generation unit that generates a clock signal, a pulse output unit that generates a pulse signal by dividing a frequency of a clock signal and outputs the pulse signal having the number of pulses and a pulse speed commanded by the CPU unit at a prescribed timing, a pulse counter that counts the number of pulses of the output pulse signal, and a processing unit that corrects the pulse speed of the pulse signal generated by the pulse output unit based on an error in the numbers of pulses.

A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, and at least one logic gate to accept the data input and delayed data output and output a logic state, wherein the logic state determines whether there is a glitch in the delayed data output, and wherein the delay circuit includes at least one delay element to register an output of the at least one logic gate at the clock edge to recognize the glitch.

A delay circuit, including a connector pad to receive a data input, a pad pin to receive a clock input having a clock edge, a first data line to receive the data input, a second data line to receive the data input, the second data line including a delay circuit that outputs a delayed data output, and at least one logic gate to accept the data input and delayed data output and output a logic state, wherein the logic state determines whether there is a glitch in the delayed data output, and wherein the delay circuit includes at least one delay element to register an output of the at least one logic gate at the clock edge to recognize the glitch.

A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.

A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.

To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

A pulse output device which corrects a pulse signal advanced or delayed from a timing prescribed by a control device and a control system including the pulse output device are provided. A PLC system including a driving device, a CPU unit, and a pulse output unit is provided. The pulse output unit includes a clock generation unit that generates a clock signal, a pulse output unit that generates a pulse signal by dividing a frequency of a clock signal and outputs the pulse signal having the number of pulses and a pulse speed commanded by the CPU unit at a prescribed timing, a pulse counter that counts the number of pulses of the output pulse signal, and a processing unit that corrects the pulse speed of the pulse signal generated by the pulse output unit based on an error in the numbers of pulses.

A wireless communication apparatus includes a memory, and a processor coupled to the memory and configured to calculate a variation amount based on a frequency difference between a first clock signal in a first synchronous processing apparatus and a second clock signal in the wireless communication apparatus according to a first message exchanged between the first synchronous processing apparatus and the wireless communication apparatus, calculate a correction amount based on a phase difference between a first time in a second synchronous processing apparatus and a second time in the wireless communication apparatus according to a second message exchanged between the second synchronous processing apparatus and the wireless communication apparatus, and when a failure is detected in the first synchronous processing apparatus based on the variation amount and the correction amount, switch an object for synchronization from the first synchronous processing apparatus to the second synchronous processing apparatus.

In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

A pulse generator comprises a circuit configured to generate a coarse pulse width (CPW) signal, a first delay unit configured to generate a first delayed coarse pulse width signal, a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal, a first analog interpolator, a second analog interpolator, and an amplifier having a first input connected to the first analog interpolator and a second input connected to the second analog interpolator and configured to generate a fine pulse width modulation signal.