An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.

A display device and a power management chip are provided. The power management chip includes a rising-edge trigger, detecting rising edges of a pulse signal; a first counter, configured to calculate the number of the rising edges; a falling-edge trigger, detecting falling edges of the pulse signal; a second counter, configured to calculate the number of the falling edges of the pulse signal; an adder, configured to sum up the number of the rising edges and the number of the falling edges of the pulse signal; and a digital-to-analog converter, electrically connected to the adder, configured to convert to a target voltage based on the sum obtained by the adder. In such a way, the poweron time of the power management chip is reduced.

A display device and a power management chip are provided. The power management chip includes a rising-edge trigger, detecting rising edges of a pulse signal; a first counter, configured to calculate the number of the rising edges; a falling-edge trigger, detecting falling edges of the pulse signal; a second counter, configured to calculate the number of the falling edges of the pulse signal; an adder, configured to sum up the number of the rising edges and the number of the falling edges of the pulse signal; and a digital-to-analog converter, electrically connected to the adder, configured to convert to a target voltage based on the sum obtained by the adder. In such a way, the poweron time of the power management chip is reduced.

The invention relates to a device for generating a plurality of clock signals or high-frequency signals. The devices includes a reference signal generator, which is connected to an oscillator and generates at its output a reference signal with a reference frequency fx. The device also includes at least one signal processor, for example, a DDS, which is connected to the reference frequency generator via a first signal line and to which the reference signal with the reference frequency fx is supplied, and which is configured to generate an output signal having a frequency less than fx.

Multiplying delay locked loops (MDLLs) with compensation for realignment error are provided. In certain implementations, an MDLL includes a control circuit, a multiplexed oscillator, and an integrate and subtract circuit. The control circuit selectively injects a reference clock signal into the multiplexed oscillator, which operates with an injected period when the reference clock signal is injected and with a natural period when the reference clock signal is not injected. The integrate and subtract circuit receives an oscillator signal from the multiplexed oscillator, and tunes an oscillation frequency of the multiplexed oscillator based on a difference between an integration of the oscillator signal over the injected period and an integration of the oscillator signal over the natural period.

In an architecture for processing data comprising a control unit and converters CN.sub.j to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edge.sub.j that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shift.sub.j furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

An optical driving device and an optical communication system are provided which can improve signal quality of laser light that uses a PAM method. A laser driver drives a semiconductor laser by using an N-level (N is an integer of 3 or more) PAM signal. A clock control circuit determines a driving timing of the laser driver. In a case where N=4, for example, the clock control circuit determines a driving timing in association with a transition of the PAM signal from a fourth level to a first level to be earlier than a driving timing in association with a transition in an opposite direction by a first time, assuming that levels are the first level, . . . , and the fourth level in an order from a level at which light intensity is minimum.

An optical driving device and an optical communication system are provided which can improve signal quality of laser light that uses a PAM method. A laser driver drives a semiconductor laser by using an N-level (N is an integer of 3 or more) PAM signal. A clock control circuit determines a driving timing of the laser driver. In a case where N=4, for example, the clock control circuit determines a driving timing in association with a transition of the PAM signal from a fourth level to a first level to be earlier than a driving timing in association with a transition in an opposite direction by a first time, assuming that levels are the first level, . . . , and the fourth level in an order from a level at which light intensity is minimum.

In an architecture for processing data comprising a control unit and converters CN.sub.j to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edge.sub.j that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shift.sub.j furthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

The invention relates to a device for generating a plurality of clock signals or high-frequency signals. The devices includes a reference signal generator, which is connected to an oscillator and generates at its output a reference signal with a reference frequency fx. The device also includes at least one signal processor, for example, a DDS, which is connected to the reference frequency generator via a first signal line and to which the reference signal with the reference frequency fx is supplied, and which is configured to generate an output signal having a frequency less than fx.