A shift register circuit including a flip-flop chain and a control circuit is provided. The flip-flop chain is configured to receive an input signal and output an output signal. The control circuit is coupled to the flip-flop chain. The control circuit is configured to receive the input signal and the output signal and output a control signal to activate the flip-flop chain according to edge transitions of the input signal and the output signal. In addition, a method for controlling a shift register circuit is also provided.

A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.

A counting device, including multiple counting circuit stages and a first logic operation circuit, is provided. The counting circuit stages are serially coupled in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. Second to Nth counting circuit stages perform counting actions according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.

A counting device, including multiple counting circuit stages and a first logic operation circuit, is provided. The counting circuit stages are serially coupled in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. Second to Nth counting circuit stages perform counting actions according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.

The system comprising a slave module and a master module. The master module comprises a master control module (CONTRM). The slave module comprises a determination module (DETER). The determination module (DETER) is configured to determine a value of a physical quantity of the slave module. The determination module (DETER) is configured to receive, from the master control module (CONTRM), a command to start counting and a command to end counting. The determination module (DETER) is configured to determine a number of oscillations, between reception of the command to start counting and reception of the command to end counting, of an oscillating signal of which a frequency depends on the value of the physical quantity.

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

The present invention provides an electronic device including a wireless communication module, a counter and a processing circuit. The wireless communication module is configured to receive a first packet and a second packet from another electronic device, wherein the first packet includes a first counter value, the second packet includes a second counter value, and the first counter value and the second counter value correspond to two adjacent edges of an original signal of another electronic device, respectively. The processing circuit is configured to obtain a third counter value from the counter when the first packet is received, and obtain a fourth counter value from the counter when the second packet is received; and the processing circuit further generates an output signal that is substantially the same as the original signal according to the first counter value, the second counter value, the third counter value and the fourth counter value.