The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.

Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.

Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.

Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.