An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

An image sensor includes a pixel sensor that senses an incident light and outputs a sampling signal of an analog shape, a sampler that compares the sampling signal and a ramp signal and outputs a comparison signal being time-axis length information, and a gray counter that counts a length of the comparison signal in synchronization with a clock signal and outputs a digital value. The gray counter includes a first flip-flop that divides the clock signal by 2 and generates a first gray code signal, a second flip-flop that delays a first data signal being a four-divided signal of the clock signal and outputs a second gray code signal, and a third flip-flop that delays the second gray code signal being two-divided and outputs a third gray code signal.

A system includes a first device to select and transmit a first code by a transmitter to a remote device; the remote device implements a sequence detector based on the first code; the transmitter in the first device generates a first sequence based on the first code; the sequence detector in the remote device detects the first sequence and activates the mechanism based on the detection; the first device may be a smartphone or a smart watch.

Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

A device (1) for delivering a signal switching from a first state to a second state, comprising: a primary circuit (4) generating a primary signal; and a secondary circuit (6) configured to: when the primary signal is initialized to the second state upon power-up, initialize a ring counter (16) to a random value in a finite sequence including a reference value, change the value of the first ring counter (16) by running through the first finite sequence in a circular fashion, and deliver at an output (3): i) a secondary signal in the first state, when the value of the first counter is different from the reference value, and ii) the primary signal, when the value of the first counter is equal to the reference value.

A device (1) for delivering a signal switching from a first state to a second state, comprising: a primary circuit (4) generating a primary signal; and a secondary circuit (6) configured to: when the primary signal is initialized to the second state upon power-up, initialize a ring counter (16) to a random value in a finite sequence including a reference value, change the value of the first ring counter (16) by running through the first finite sequence in a circular fashion, and deliver at an output (3): i) a secondary signal in the first state, when the value of the first counter is different from the reference value, and ii) the primary signal, when the value of the first counter is equal to the reference value.

An integrated circuit is provided. The integrated circuit includes: a clock source configured to: generate a clock signal of the integrated circuit; at least two functional circuits; and at least two clock generators corresponding to the functional circuits and configured to: determine initial phases of the corresponding functional circuits, and generate clock signals of the functional circuits based on the clock signal of the integrated circuit and the initial phases, so as to keep the clock signals of all the functional circuits synchronized, wherein the initial phases are determined based on transmission distances, over which the clock signal of the integrated circuit is transmitted from the clock source to the functional circuits, and loads of the functional circuits.

The driver circuit according to the invention includes a receiver module, a counter unit, isolation units and a voltage regulation unit. The receiver module receives an initiation signal and performs filtering using a low-pass filter to convert the initiation signal into a driving signal which is transmitted to the counter unit. Upon receiving the driving signal, the output terminals of the counter unit are sequentially activated to output a control signal. The isolation units may be diodes or transistors adapted to output an isolated control signal. The voltage regulation unit includes a plurality of resistors and is adapted to output a control voltage corresponding to one of the resistors according to the isolated control signal. The control voltage is useful in shifting the operation of an electrical device from one operation state to another.

Digital n-state switching devices are characterized by n-state switching tables with n greater than 4. N-state switching tables are transformed by a Finite Lab-transform (FLT) into an FLTed n-state switching table. Memory devices, processors and combinational circuits with inputs and an output are characterized by an FLTed n-state switching table and perform switching operations between physical states in accordance with an FLTed n-state switching table. The devices characterized by FLTed n-state switching tables are applied in cryptographic devices. The cryptographic devices perform standard cryptographic operations or methods that are modified in accordance with an FLT. One or more standard cryptographic methods are specified in Federal Information Processing Standard (FIPS) Publications. Security is improved by at least a factor n.sup.2.

Digital n-state switching devices are characterized by n-state switching tables with n greater than 4. N-state switching tables are transformed by a Finite Lab-transform (FLT) into an FLTed n-state switching table. Memory devices, processors and combinational circuits with inputs and an output are characterized by an FLTed n-state switching table and perform switching operations between physical states in accordance with an FLTed n-state switching table. The devices characterized by FLTed n-state switching tables are applied in cryptographic devices. The cryptographic devices perform standard cryptographic operations or methods that are modified in accordance with an FLT. One or more standard cryptographic methods are specified in Federal Information Processing Standard (FIPS) Publications. Security is improved by at least a factor n.sup.2.