An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

A correction arithmetic circuit disclosed herein includes an offset temperature characteristic correction unit that corrects an offset temperature characteristic of an input signal according to an input signal characteristic at a specific temperature and a temperature characteristic at a specific input signal. A signal processor disclosed herein includes a pulse count number setting circuit that generates a pulse count number setting signal in accordance with an input signal and a pulse generation unit that generates a pulse signal by counting a pulse number of a reference clock signal according to the pulse count number setting signal. The pulse count number setting circuit corrects the pulse count number setting signal so as to cancel a frequency temperature characteristic of the pulse signal.

A frequency divider includes a first shifter and a second shifter. The first shifter includes first to M-th clock control components connected together to form a first ring. The control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring. An output of selected clock control components in the first shifter is provided as a carry signal of the first shifter. The second shifter includes first to N-th clock control components connected together to form a second ring. The control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring. An output of selected clock control components in the second shifter is provided as a carry signal of the second shifter. M and N are integers greater than one.

A technique includes driving a node of a stage of a ring counter to a predetermined signal state; and clocking the ring counter to cause the signal state to propagate to at least one additional stage of the ring counter to initialize the ring counter with a reset sequence.

A correction arithmetic circuit disclosed herein includes an offset temperature characteristic correction unit that corrects an offset temperature characteristic of an input signal according to an input signal characteristic at a specific temperature and a temperature characteristic at a specific input signal. A signal processor disclosed herein includes a pulse count number setting circuit that generates a pulse count number setting signal in accordance with an input signal and a pulse generation unit that generates a pulse signal by counting a pulse number of a reference clock signal according to the pulse count number setting signal. The pulse count number setting circuit corrects the pulse count number setting signal so as to cancel a frequency temperature characteristic of the pulse signal.

A correction arithmetic circuit disclosed herein includes an offset temperature characteristic correction unit that corrects an offset temperature characteristic of an input signal according to an input signal characteristic at a specific temperature and a temperature characteristic at a specific input signal. A signal processor disclosed herein includes a pulse count number setting circuit that generates a pulse count number setting signal in accordance with an input signal and a pulse generation unit that generates a pulse signal by counting a pulse number of a reference clock signal according to the pulse count number setting signal. The pulse count number setting circuit corrects the pulse count number setting signal so as to cancel a frequency temperature characteristic of the pulse signal.