An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.

In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

A ring oscillator including: an oscillation circuit including an even number of inverters connected in a ring configuration, the oscillation circuit outputting a clock signal; plural potential fixing circuits respectively connected between pairs of the inverters, each of plural potential fixing circuits being switchable between a connected and a disconnected state in response to a first control signal; and an adjustment circuit that adjusts a drive capability of the inverters based on a second control signal, wherein, during startup, the drive capability is controlled to be a first capability, in which the potential fixing circuits are connected, by the first control signal, and wherein, after a predetermined time has elapsed after the first control signal is output, the drive capability is controlled to be a second capability, higher than the first capability, in which the potential fixing circuits are disconnected, by the second control signal.

A ring oscillator including: an oscillation circuit including an even number of inverters connected in a ring configuration, the oscillation circuit outputting a clock signal; plural potential fixing circuits respectively connected between pairs of the inverters, each of plural potential fixing circuits being switchable between a connected and a disconnected state in response to a first control signal; and an adjustment circuit that adjusts a drive capability of the inverters based on a second control signal, wherein, during startup, the drive capability is controlled to be a first capability, in which the potential fixing circuits are connected, by the first control signal, and wherein, after a predetermined time has elapsed after the first control signal is output, the drive capability is controlled to be a second capability, higher than the first capability, in which the potential fixing circuits are disconnected, by the second control signal.

In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.

A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

A radar apparatus includes a transmitter including a plurality of circuits that intermittently transmit one or more radar signals, the plurality of circuits being suspended power supplying during a period in which the one or more radar signals are not transmitted, variation detection circuitry that detects process variations of the plurality of circuits, and determination circuitry that determines a startup timing of each of the plurality of circuits in response to the process variations and outputs startup commands in response to the determined startup timings to the plurality of circuits.

A radar apparatus includes a transmitter including a plurality of circuits that intermittently transmit one or more radar signals, the plurality of circuits being suspended power supplying during a period in which the one or more radar signals are not transmitted, variation detection circuitry that detects process variations of the plurality of circuits, and determination circuitry that determines a startup timing of each of the plurality of circuits in response to the process variations and outputs startup commands in response to the determined startup timings to the plurality of circuits.