A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed. current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.

A phase synchronization circuit includes: an oscillation circuit that includes a variable current generation unit that generates a variable current of a current amount corresponding to a control voltage and a fixed current generation unit that generates a fixed. current of a current amount corresponding to a correction code and generates an output clock signal having a frequency corresponding to the total current amount of the variable current and the fixed current; a feedback circuit that generates a feedback clock signal based on the output clock signal; a control voltage generation circuit that generates the control voltage to make a frequency of the output clock signal become a desired frequency in a normal operation mode; and a correction code generation circuit that generates the correction code in a calibration mode, in which in the calibration mode, the control voltage generation circuit outputs a fixed one of the control voltage.

According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.

According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.

A system comprises a first comparator, a second comparator, a pulse-width modulation (PWM) controller, and a ramp generator. The first comparator has a positive input coupled to a first ramp output of the ramp generator and a negative input configured to receive an input voltage. The second comparator has a positive input configured to receive the input voltage and a negative input coupled to a second ramp output of the ramp generator. The PWM controller is coupled to outputs and control signal inputs of the first and second comparators and has a control output. In some implementations, the ramp generator generates a high-side falling ramp for the first comparator and a low-side rising ramp for the second comparator. In some implementations, the ramp generator includes a first ramp generator for the high-side falling ramp and a second ramp for the low-side rising ramp.

A system comprises a first comparator, a second comparator, a pulse-width modulation (PWM) controller, and a ramp generator. The first comparator has a positive input coupled to a first ramp output of the ramp generator and a negative input configured to receive an input voltage. The second comparator has a positive input configured to receive the input voltage and a negative input coupled to a second ramp output of the ramp generator. The PWM controller is coupled to outputs and control signal inputs of the first and second comparators and has a control output. In some implementations, the ramp generator generates a high-side falling ramp for the first comparator and a low-side rising ramp for the second comparator. In some implementations, the ramp generator includes a first ramp generator for the high-side falling ramp and a second ramp for the low-side rising ramp.

A pulse width modulation (PWM) method for converting an input signal into an output PWM signal includes the following steps: generating a first linear periodic wave and a second linear periodic wave which are triangle waves or sawtooth waves, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave; determining whether the level of the input signal is lower than a light load threshold; when the level of the input signal is lower than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the second linear periodic wave; and when the level of the input signal is higher than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the first linear periodic wave.

A pulse width modulation (PWM) method for converting an input signal into an output PWM signal includes the following steps: generating a first linear periodic wave and a second linear periodic wave which are triangle waves or sawtooth waves, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave; determining whether the level of the input signal is lower than a light load threshold; when the level of the input signal is lower than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the second linear periodic wave; and when the level of the input signal is higher than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the first linear periodic wave.

A clock generation circuit coupled to an integrator circuit uses a variable resistance that is adjusted in a transconductance bias feedback circuit. This resistance is calibrated to the reciprocal of the transconductance of the input amplifier. The product of the adjusted resistance and a capacitance in the clock generation circuit provides a time constant for the settling time of the integrator and controls a pulse width of an adaptively controlled duty cycle output clock.

A clock generation circuit coupled to an integrator circuit uses a variable resistance that is adjusted in a transconductance bias feedback circuit. This resistance is calibrated to the reciprocal of the transconductance of the input amplifier. The product of the adjusted resistance and a capacitance in the clock generation circuit provides a time constant for the settling time of the integrator and controls a pulse width of an adaptively controlled duty cycle output clock.