This application relates an activity detector (100) for detecting signal activity in an input audio signal (S.sub.IN), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator (201) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM (103) having a second hysteretic comparator (401) is arranged to receive a reference voltage (V.sub.MID) and generate a clock signal (S.sub.CLK). A time-decoding converter (102) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor (104) is responsive to a count signal (S.sub.CT) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

An electronic fuse for a power supply includes at least two switching elements and a regulation unit, wherein a first switching element is arranged in a main branch, where the regulation unit is switches off the first switching element when a predetermined threshold value is exceeded by a prevailing current value, and a second switching element that is also actuated by the regulation unit, which is arranged in an auxiliary branch parallel to the first switching element and assumes a substantial proportion of a resulting power loss when an overload occurs, and the second switching element, which is arranged in at least one auxiliary branch, is configured or optimized for linear operation, and where the at least two switching elements are configured such that the line resistance of the second switching element is at least twice the line resistance of the first switching element.

A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

A method for controlling a stepper motor includes calculating a duty cycle of a current provided to the stepper motor and comparing a difference, between the calculated duty cycle and a base duty cycle of current provided to the stepper motor under a base load condition, to a reference duty cycle value. The method also includes adjusting a peak current level of the current provided to the stepper motor responsive to the comparison.

Systems and methods are provided for implementing a hardware accelerator. The hardware accelerator emulates a neural network, and includes a memristor crossbar array, and a non-linear filter. The memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The non-linear filter is coupled to the memristor crossbar array and programmed to harness noise signals that may be present in analog circuitry of the hardware accelerator. The noise signals can be harnessed such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values. In some embodiments, the non-liner filter is implemented as a Schmidt trigger comparator.

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

An embodiment of the present disclosure relates to a circuit of cyclic activation of an electronic function comprising a hysteresis comparator controlling the charge of a capacitive element powering the function.

A spike suppression circuit includes a wide bandgap transistor, a first transistor, a clamping circuit, and a capacitor. The wide bandgap transistor is depletion-type. The first transistor is coupled in series with the wide bandgap transistor. The clamping circuit provides a voltage difference, and is coupled to a common node between the wide bandgap transistor and the first transistor. The capacitor provides a supply voltage for the clamping circuit. When the first transistor is turned off, the capacitor can recycle spike energy at the common node.

Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.