A retention flip-flop includes a master latch outputting a first signal which is generated based on a signal inputted through an input terminal based on first control signals; a slave latch outputting a second signal generated based on the first signal based on the first control signals and second control signals; and a control logic that generates the first control signals based on a clock signal and provides the first control signals to the master latch and the slave latch, and generates the second control signals based on a power down signal and provides the second control signals to the slave latch. The slave latch comprises a retention latch which transmits the first signal to an output terminal as the second signal by operating as an open loop based on the second control signals or maintains the second signal by forming a closed loop based on the second control signals.

A clocked storage element comprises a first latch having an input data node, a clock input node and a first latch output data node, and a second latch having an input connected to the first latch output data node, a clock input node and a second latch output data node. The first and second latches can have a clocked pull-up current path consisting of two p-channel transistors between their respective output data nodes and the VDD supply line, and a clocked pull-down current path consisting of two n-channel transistors between their respective output data nodes and the VSS supply line.

A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.

A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

An error detection and correction method is provided. The method includes: when a pipeline stage error is detected, correcting the pipeline stage error; when it is determined that a plurality of cascaded pipeline stage circuits have continuous pipeline stage errors, stopping all operations of all pipeline stage circuits; flushing the data of the pipeline stage circuits; and re-processing the data of the pipeline stage circuits at a downclocked frequency.

A master-slave flip-flop includes a first latch, a second latch and a tristate driver. The first latch has a combined input/output that is coupled with a common node, a pm output, and an nm output. The tristate driver has pm and nm inputs coupled with the pm and nm outputs of the first latch, and a tristate output coupled with the common node. A pm input signal prevents the tristate driver from pulling the common node high, and an nm input signal prevents the tristate driver from pulling the common node low. The second latch is directly coupled with the common node. The first latch generates an nm signal and a pm signal in response to a signal on the first latch clk input and a state of the common node, wherein the pm signal and the nm signal have opposite polarities when the signal on the first latch clk input has a first value, and equal polarities when the signal on the first latch clk input has a second value.

A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.

A range sensor and a method thereof. The range sensor includes a light source configured to project a plurality of sheets of light at an angle within a field of view (FOV); an image sensor, wherein the image sensor is offset from the light source; collection optics; and a controller connected to the light source, the image sensor, and the collection optics, and configured to simultaneously determine a range of a distant object based on direct time-of-flight (TOF) and a range of a near object based on triangulation.