A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

A sense enable circuit for enabling a sense amplifier is provided. The sense enable circuit includes a signal generator circuit, a group of reference memory cells and a control circuit. The signal generator circuit is configured to generate a sense amplifier enable signal according to a trigger signal. The sense amplifier is enabled by the sense amplifier enable signal to sense data stored in a memory cell. Each reference memory cell is coupled to a reference wordline and a reference bitline. The reference wordline is activated in response to activation of a wordline coupled to the memory cell. The reference memory cell is configured to, in response to activation of the reference wordline, couple a first reference signal to the reference bitline. The control circuit is configured to adjust a signal level of the reference bitline, and generate the trigger signal according to the signal level of the reference bitline.

An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

In one example, a switched circuit includes first and second transistors. The first transistor has a first gate and a first source/drain path. The second transistor has a second gate and a second source/drain path. The first and second source/drain paths are coupled in series between an input terminal and an output terminal. A first drive circuit has a first drive input and a first drive output. A second drive circuit has a second drive input and a second drive output. The first drive output is coupled to the first gate, and the second drive output is coupled to the second gate. Switching circuitry is coupled between: at least one of first or second power supply circuits; and at least one of the first or second drive circuits.

A control system for a machine having at least one control element is disclosed. The control system includes multiple input sensors in communication with the control element. The input sensor generates an input signal based on an input to the control element. The control system includes multiple actuating members to control operations of the machine. The control system includes a controller in communication with the input sensors and the actuating members. The controller receives the input signal from the input sensor and determines an imposed hysteresis level corresponding to the input signal based on a hysteresis input function. The controller is further configured to generate a hysteresis conditioned input signal based on the imposed hysteresis level.

Various embodiments of the present invention relate to a power amplification device and method, wherein the power amplification device can comprise: a power amplifier; a switch mode converter for controlling a bias of the power amplifier; a comparator for providing a switching signal to the switch mode converter according to an envelope signal; and a control unit for determining whether a switching frequency of the switch mode converter is within a specific band and applying an offset to the switching frequency so as to deviate from the specific band if the switching frequency of the switch mode converter is within the specific band. Various other embodiments can be carried out.

A voltage supply circuit for an electronic circuit includes a switch configured to selectively connect a supply input of the electronic circuit with a main supply voltage source. An auxiliary voltage supply unit has an auxiliary voltage output coupled to the supply input of the electronic circuit. The auxiliary voltage supply unit is configured to at least temporarily output an auxiliary voltage to the supply input. The auxiliary voltage has a voltage level lower than a voltage level of a main supply voltage supplied by the main supply voltage source.

This disclosure relates to systems and/or methods for subtracting in the current domain an output current primary signal from a primary sensor from an output current reference signal from a reference sensor to produce a frequency output signal indicative of the difference between the output current primary signal and the output current reference signal.

This disclosure relates to a dual power supply detection circuit including first and second input stage field effect transistors, an inverter stage, a feedback stage field effect transistor, and first and second compensation circuits. The inverter stage includes a complimentary pair of transistors, and the complementary pair of transistors includes an NMOS transistor and a PMOS transistor configured and arranged so that gate lengths of the PMOS and NMOS transistors are different. The disclosure also relates to an integrated circuit including a dual power supply detection circuit.

When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.