An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

A voltage generating circuit includes a first transistor and a second transistor. Voltage of a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the voltage generating circuit. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as an output of the voltage generating circuit. A gate of the second transistor is connected to a drain of the second transistor.

A method for detecting and correcting an error in a circuit is provided. The circuit is configured to receive an input signal and clock the input signal with a rising and falling timing signal. The method includes detecting late arrival signal transition of the input signal, at an intermediate point of a path, the path being one through which the input signal transits. The method further includes predicting an error in the input signal in response to detecting the late arrival signal transition at the intermediate point of the path. In addition, the method includes correcting the error in the input signal by manipulating the timing signal and/or a supply voltage.

A voltage generating circuit includes a first transistor and a second transistor. Voltage of a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the voltage generating circuit. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as an output of the voltage generating circuit. A gate of the second transistor is connected to a drain of the second transistor.

An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.

An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.

An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.

An integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. In the control circuit, a first switch is electrically connected to a second switch at a buffer output node. The control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.

An integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. In the control circuit, a first switch is electrically connected to a second switch at a buffer output node. The control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.

An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.