A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.

A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

The present technology includes a replica circuit and an oscillator including the same. The replica circuit includes a first terminal to which a replica voltage having a positive voltage is supplied, a second terminal to which a ground voltage is supplied, a replica main circuit connected between the first terminal and the second terminal and configured to form a first current path in response to the replica voltage, and a replica sub circuit connected in parallel with the replica main circuit between the first terminal and the second terminal and configured to form a second current path in response to the replica voltage. A current flowing through the second current path having a replica sub current amount is less than a current flowing through the first current path having a replica main current amount.

The present technology includes a replica circuit and an oscillator including the same. The replica circuit includes a first terminal to which a replica voltage having a positive voltage is supplied, a second terminal to which a ground voltage is supplied, a replica main circuit connected between the first terminal and the second terminal and configured to form a first current path in response to the replica voltage, and a replica sub circuit connected in parallel with the replica main circuit between the first terminal and the second terminal and configured to form a second current path in response to the replica voltage. A current flowing through the second current path having a replica sub current amount is less than a current flowing through the first current path having a replica main current amount.