In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.

In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.

A disclosed pre-driver circuit includes multiple signal generation stages configured to receive different bias voltages from local switching bias circuit(s). In some embodiment, pre-driver circuit has multiple switching bias circuits, each with a bias voltage node connected to a corresponding stage. In other embodiments, the pre-driver circuit has a single switching bias circuit with multiple bias voltage nodes and a multi-input/multi-output multiplexor with inputs connected to the bias voltage nodes and outputs connected to the stages. The switching bias circuit(s) and a primary inverter in each stage all receive the same input signal. When this input signal transitions, the switching bias circuit(s) supply bias voltages to the stages and the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated by the different stages transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the switching bias circuit(s) turn off.

A disclosed pre-driver circuit includes multiple signal generation stages configured to receive different bias voltages from local switching bias circuit(s). In some embodiment, pre-driver circuit has multiple switching bias circuits, each with a bias voltage node connected to a corresponding stage. In other embodiments, the pre-driver circuit has a single switching bias circuit with multiple bias voltage nodes and a multi-input/multi-output multiplexor with inputs connected to the bias voltage nodes and outputs connected to the stages. The switching bias circuit(s) and a primary inverter in each stage all receive the same input signal. When this input signal transitions, the switching bias circuit(s) supply bias voltages to the stages and the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated by the different stages transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the switching bias circuit(s) turn off.

In some examples, a pulser circuit is configured to provide a pulse signal in a first operational state, pre-charge components of the pulser circuit via a first signal path in a second operational state following the first operational state, wherein the first signal path includes first components having a first voltage tolerance and second components having a second voltage tolerance, the first voltage tolerance being less than the second voltage tolerance, and discharge a voltage of the pulser circuit to ground in a third operational state between the first operational state and the second operational state, and following the second operational state.

In some examples, a pulser circuit is configured to provide a pulse signal in a first operational state, pre-charge components of the pulser circuit via a first signal path in a second operational state following the first operational state, wherein the first signal path includes first components having a first voltage tolerance and second components having a second voltage tolerance, the first voltage tolerance being less than the second voltage tolerance, and discharge a voltage of the pulser circuit to ground in a third operational state between the first operational state and the second operational state, and following the second operational state.

In various embodiments, a master-slave clock generation circuit may include a first delay circuit, a second delay circuit, a first tristate inverter, and a second tristate inverter. The first delay circuit may delay a clock signal and output a slave clock signal and a delayed clock signal. The first tristate inverter may selectively invert the clock signal based on a scan enable signal. The second tristate inverter may selectively invert the delayed clock signal based on the scan enable signal. The second delay circuit may delay a signal received from the first tristate inverter, the second tristate inverter, or both, and output a master clock signal. As a result, the master-slave clock generation circuit may be configured to output a master clock signal and a slave clock signal having differing sets of relative timing characteristics depending on whether the scan enable signal is asserted.

In various embodiments, a master-slave clock generation circuit may include a first delay circuit, a second delay circuit, a first tristate inverter, and a second tristate inverter. The first delay circuit may delay a clock signal and output a slave clock signal and a delayed clock signal. The first tristate inverter may selectively invert the clock signal based on a scan enable signal. The second tristate inverter may selectively invert the delayed clock signal based on the scan enable signal. The second delay circuit may delay a signal received from the first tristate inverter, the second tristate inverter, or both, and output a master clock signal. As a result, the master-slave clock generation circuit may be configured to output a master clock signal and a slave clock signal having differing sets of relative timing characteristics depending on whether the scan enable signal is asserted.