A method for operating a drive unit having an active element with a resonator and an excitation structure for exciting oscillations in the resonator and thereby driving a passive element. The method includes driving the excitation structure with a driving signal, the driving signal being a periodic signal having driving pulses repeated with an excitation frequency. Depending on a control signal, modifying the driving signal, if the control signal is within a first range, by modifying the excitation frequency or modifying the shape of the driving pulses and, if the control signal is within a second range, repeatedly omitting driving pulses.

According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.

According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.