Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

An oscillation circuit includes resistors with tap points for high/low reference voltages. An RC network coupled in parallel with the resistors includes a first capacitor to vary a first voltage input and a second capacitor to generate a second voltage input. A first comparator alternately compares the voltage inputs with the low reference voltage to generate oscillation outputs. A PTAT current DAC supplies an injection current to a resistor of the series of resistors that variably modulates the reference voltages. A second comparator alternately compares the voltage inputs with the high reference voltage and controls generation of an adaptive bias current to first comparator near a switching threshold voltage range thereof. A chop switch matrix alternately flips voltage reference inputs to input terminals of first comparator. A multiplexer alternately inverts a polarity of the oscillation outputs in concert with alternately flipping the voltage reference inputs by the chop switch matrix.

An oscillator circuit includes a first comparator that outputs a first signal indicative of a comparison result between an input potential and a threshold, a second comparator that outputs a second signal indicative of a comparison result between an input potential and the threshold, a RS flip-flop circuit that receives the first signal and the second signal and outputs first and second oscillation signals, a first charge/discharge unit that charges and discharges a first capacitor based on the first oscillation signal, a second charge/discharge unit that charges and discharges a second capacitor based on the second oscillation signal, a first dummy switch controlled to be on and off according to the second oscillation signal and adding a predetermined capacity to a first node, and a second dummy switch controlled to be on and off according to the first oscillation signal and adding a predetermined capacity to a second node.

Relaxation oscillator and method for providing an output frequency. For example, the relaxation oscillator includes a reference generator, a capacitor, a first comparator, a second comparator, a latch, and a temperature compensation circuit. The reference generator is configured to generate a first bias current, a first bias voltage and a second bias voltage. The capacitor is configured to be charged by a charging current to generate a charged voltage, and the charging current is generated based on at least the first bias current. The first comparator is configured to compare the charged voltage and the first bias voltage to generate a first comparison result, and the second comparator is configured to compare the charged voltage and the second bias voltage to generate a second comparison result. The latch is configured to generate a clock signal based on at least the first comparison result and the second comparison result.

A triangular wave generator includes a wave generator configured to generate a triangular wave according to a clock signal and a control signal. The triangular wave generator further includes a wave controller configured to adjust a value of the control signal in a correction mode. The control signal includes a first bias control signal, a second bias control signal, and a capacitance control signal.

A triangular wave generator includes a wave generator configured to generate a triangular wave according to a clock signal and a control signal. The triangular wave generator further includes a wave controller configured to adjust a value of the control signal in a correction mode. The control signal includes a first bias control signal, a second bias control signal, and a capacitance control signal.

A pulse-width modulation circuit includes an oscillator stage. The oscillator stage includes a first voltage comparator having a first input terminal, a second input terminal and an output terminal. A first capacitor is coupled to the first input terminal of the first voltage comparator. A charging path for the first capacitor is coupled between the first capacitor and the output terminal of the first voltage comparator, the charging path having a first resistance. A discharging path for the first capacitor is coupled between the first capacitor and the output terminal of the first voltage comparator, the discharging path having a second resistance that is different from the first resistance. A duty cycle of a clock signal generated by the oscillator stage is determined based on a first RC time constant for charging the first capacitor and a second RC time constant for discharging the first capacitor.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a comparator stage, a resistor, a capacitor, and active switches arranged to provide a clock signal having a time period that is independent of a first source voltage. Independence may be achieved by using a second source voltage derived from the first source voltage as a fixed ratio.

An oscillator circuit includes an initial level setting circuit configured to operate in an on-state during an initial operation of the oscillator circuit to supply a first level voltage to a first node and a second level voltage to a second node, a switching circuit configured to connect a power supply voltage terminal and a ground terminal to the first or second node in response to first and second clock signals having different phases after the initial operation, a signal generation circuit connected between the first and second nodes and configured to perform charging and discharging operations based on a potential difference between the first and second nodes, and generate first and second voltages determined by the charging and discharging operations, and an inverter circuit configured to generate the first clock signal based on the first voltage, and generate the second clock signal based on the second voltage.

Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.