To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

A clamp circuit includes a first MOS transistor and a second MOS transistor connected in series with the first MOS transistor. The first MOS transistor has a gate connected to a drain of the first MOS transistor. The second MOS transistor has a gate connected to a drain of the second MOS transistor. The clamp circuit is configured so that at least one of the first MOS transistor and the second MOS transistor causes a body effect.

A switching gate driver and method of operating the gate driver is described. The gate driver includes a first voltage source, and a clamping voltage source configured to have a voltage that is less than that of the first voltage source. There is also a current path, for initial charging of a gate voltage of the switching gate, between the first voltage source and a ground source; and a comparator which is configured to clamp the gate voltage to the clamping voltage source as it approaches the voltage of said clamping voltage source.

A semiconductor assembly includes a first FET integrated within the semiconductor assembly and comprising gate, source and drain terminals. The semiconductor assembly further includes a low voltage switching device integrated within the semiconductor assembly and being configured to electrically short a gate-source capacitance of the first FET responsive to a control signal.

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

A signal analysis method for analyzing a pulse modulated input signal is described. The signal analysis method includes: receiving the pulse modulated input signal, the input signal including a symbol sequence; recovering a clock signal from the input signal, the clock signal being associated with the input signal; sampling the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time; determining at least two different levels of input signal samples being associated with different symbols of the symbol sequence; and determining at least one decision threshold based on the at least two different levels determined previously, the decision threshold being associated with a symbol transition of the symbol sequence. Further, a signal analysis apparatus is described.

A signal analysis method for analyzing a pulse modulated input signal is described. The signal analysis method includes: receiving the pulse modulated input signal, the input signal including a symbol sequence; recovering a clock signal from the input signal, the clock signal being associated with the input signal; sampling the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time; determining at least two different levels of input signal samples being associated with different symbols of the symbol sequence; and determining at least one decision threshold based on the at least two different levels determined previously, the decision threshold being associated with a symbol transition of the symbol sequence. Further, a signal analysis apparatus is described.

The present invention provides a voltage monitoring apparatus capable of stable operation even in a low-voltage region. The voltage monitoring apparatus (1) includes: an inner voltage generating portion (40), lowering an input voltage (VIN) to generate an inner voltage (Vreg); an input voltage monitoring portion (30), receiving a power supply from an output terminal of the inner voltage generating portion (40) to operate; a switch portion (50), disposed between an input terminal of the input voltage (VIN) and the output terminal of the inner voltage generating portion (40); and a switch driving portion (60), turning on the switch portion (50) when the input voltage (VIN) is lower than a threshold voltage (for example, Vy<Vref), and turning off the switch portion (50) when the input voltage (VIN) is higher than the threshold voltage (for example, Vy>Vref). Furthermore, the threshold voltage is preferably set as, for example, turning off the switch portion (50) upon the inner voltage generating portion (40) changing to a state capable of outputting the inner voltage (Vreg) that is at least higher than a minimum operating voltage of the input voltage monitoring portion (30).