A comparator circuit with dynamic biasing comprises a comparator, first dynamic biasing generator, first extra biasing device, second dynamic biasing generator, and second extra biasing device. The comparator includes a biasing circuit, input stage, active loads, and output terminal. The input stage has a first input terminal, second input terminal, first current path, and second current path. The comparator is configured to output an output signal at the output terminal according to the first input signal and second input signal. The first dynamic biasing generator is coupled between a first detection node and the first extra biasing device coupled to the biasing circuit. The second dynamic biasing generator is coupled between a second detection node and the second extra biasing device coupled to the biasing circuit. The first and second detection nodes are between the input stage and the active loads.

A circuit for processing a logic input, including a first comparator capable of comparing the logic input with a first reference voltage and of providing a logic output at a first output logic level if the logic input is higher than the first reference voltage and otherwise at a second output logic level different from the first output logic level. The power supply of the first comparator and the first voltage reference are activated by the logic input.

A comparator circuit's signal range can be enhanced using an input signal attenuation circuit. In an example, a comparator circuit receives an input signal and a reference signal. The input signal can be conditioned by one or both of the attenuation circuit and a conditioning circuit, and a resulting conditioned signal can be presented to a compare element. Under first operating conditions where the input signal is approximately equal to the reference signal, the attenuation circuit can be substantially bypassed and a first resulting conditioned signal can be presented to the compare element. Under second operating conditions where the input signal is substantially greater than the reference signal, the attenuation circuit receives a portion of the input signal and a different second resulting conditioned signal can be presented to the compare element.

A comparator includes: a first selector for selecting one of a first reference voltage and a first correction reference voltage, based on a first determination value of data at a past time of a first adjacent channel; a first comparator for comparing the difference between a voltage selected from the first reference voltage and the first correction reference voltage and a second reference voltage with an input voltage at a current time of a target channel; and a first output unit for determining an output voltage at the current time of the target channel, based on the comparison result of the first comparator.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

Methods, apparatus, and systems are disclosed for voltage supervisors. An example apparatus includes a first switch having a first source, a first drain, and a first gate, a first resistor having a first terminal and a second terminal, the first terminal coupled to the first source and second terminal coupled to the first drain, a second resistor having a third terminal and a fourth terminal, the third terminal coupled to the second terminal, a third resistor having a fifth terminal and a sixth terminal, the fifth terminal coupled to the fourth terminal, a fourth resistor having a seventh terminal and an eighth terminal, the seventh terminal coupled to the sixth terminal, a second switch having a second source, a second drain, and a second gate, the second source coupled to the seventh terminal, and a comparator having an output, the output coupled to the first gate and the second gate.

A circuit for processing a logic input, including a first comparator capable of comparing the logic input with a first reference voltage and of providing a logic output at a first output logic level if the logic input is higher than the first reference voltage and otherwise at a second output logic level different from the first output logic level. The power supply of the first comparator and the first voltage reference are activated by the logic input.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

Methods, apparatus, and systems are disclosed for voltage supervisors. An example apparatus includes a first switch having a first source, a first drain, and a first gate, a first resistor having a first terminal and a second terminal, the first terminal coupled to the first source and second terminal coupled to the first drain, a second resistor having a third terminal and a fourth terminal, the third terminal coupled to the second terminal, a third resistor having a fifth terminal and a sixth terminal, the fifth terminal coupled to the fourth terminal, a fourth resistor having a seventh terminal and an eighth terminal, the seventh terminal coupled to the sixth terminal, a second switch having a second source, a second drain, and a second gate, the second source coupled to the seventh terminal, and a comparator having an output, the output coupled to the first gate and the second gate.

A circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on the peak detector output proportional to a lowest voltage on the peak defector input. The anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp a voltage on the peak detector input responsive to a voltage on the diode's anode being greater than the lowest voltage on the peak detector's input. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.