The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

An integrated circuit transceiver device includes a plurality of functional circuits, and clock circuitry for distributing synchronous, in-phase, phase-locked clock signals to all transceiver circuits. The clock circuitry includes a frequency-controllable distributed oscillator including at least one coupled pair of transmission line oscillators having a respective oscillator core, and at least one respective transmission line segment. At least one impedance element couples the at least one respective transmission line segment of a first transmission line oscillator to the at least one respective transmission line segment of a second transmission line oscillator. Impedance of the impedance element is different from impedance of each respective transmission line segment to cause reflection at the at least one impedance element. At least one tap corresponding to each respective one of the transmission line oscillators outputs synchronous, in-phase, phase-locked clock signals for the functional circuits at points along the distributed oscillator.

An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.

An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

A voltage-controlled oscillator, including a voltage-controlled LC resonator including at least one first output node; an amplifier including at least one first dual-gate MOS transistor including first and second gates, coupling the first output node to a second node of application of a reference potential; and a regulation circuit capable of applying to the second gate of the first transistor a bias voltage variable according to the amplitude of the oscillations of a signal delivered on the first output node of the oscillator.

The invention provides a method for calibrating crystal frequency offset through an internal loop of a central processing unit (CPU), which comprises: outputting an oscillation exciting signal to a crystal circuit by the CPU; producing a clock signal by the crystal circuit; outputting the clock signal through an output port arranged on the CPU by the internal loop; and adopting and connecting a frequency meter to the output port, and receiving and testing the clock signal to obtain a testing result; determining whether a deviation of the clock signal is qualified; if it is qualified, the tester exits subsequently, otherwise the tester regulates the crystal circuit, and then turning to Step S4. The clock signal of the CPU is output at the output port through the internal loop, and then the frequency meter is used for measuring the clock without being influenced by a probe, and the measurement is more accurate.

The invention provides a method for calibrating crystal frequency offset through an internal loop of a central processing unit (CPU), which comprises: outputting an oscillation exciting signal to a crystal circuit by the CPU; producing a clock signal by the crystal circuit; outputting the clock signal through an output port arranged on the CPU by the internal loop; and adopting and connecting a frequency meter to the output port, and receiving and testing the clock signal to obtain a testing result; determining whether a deviation of the clock signal is qualified; if it is qualified, the tester exits subsequently, otherwise the tester regulates the crystal circuit, and then turning to Step S4. The clock signal of the CPU is output at the output port through the internal loop, and then the frequency meter is used for measuring the clock without being influenced by a probe, and the measurement is more accurate.

An electronic device includes: a first input node configured to receive a dock signal; a second input node configured to receive an activation signal or a deactivation signal; a filter circuit responsive to: (a) the activation signal to activate the filter circuit to block the dock signal; or (b) the deactivation signal to deactivate the filter circuit to pass the dock signal; and an output node configured for coupling to a synchronous I/O interface of an integrated circuit to control operation of the synchronous I/O interface.