A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

A charge pump device includes first to third current source circuits, a first switch, and a second switch. The first current source circuit is implemented with a first type transistor, and provides a first current to an output node. The first switch is selectively turned on according to a first control signal. When the first switch is turned on, the second current source circuit drains a second current from the output node. The second switch is selectively turned on according to a second control signal. Each of the first switch and the second switch is implemented with a second type transistor, and a withstand voltage of the first type transistor is higher than a withstand voltage of the second type transistor. When the second switch is turned on, the third current source circuit drains a third current from the output node.

A charge pump device includes first to third current source circuits, a first switch, and a second switch. The first current source circuit is implemented with a first type transistor, and provides a first current to an output node. The first switch is selectively turned on according to a first control signal. When the first switch is turned on, the second current source circuit drains a second current from the output node. The second switch is selectively turned on according to a second control signal. Each of the first switch and the second switch is implemented with a second type transistor, and a withstand voltage of the first type transistor is higher than a withstand voltage of the second type transistor. When the second switch is turned on, the third current source circuit drains a third current from the output node.

A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.

A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.

A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.

An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

Systems and methods are provided for a cascade phase locked loop. A first phase locked loop receives a reference clock signal having a first frequency and generates a high frequency clock signal that is phase aligned with the reference clock signal. A first divider divides the high frequency clock signal to generate a middle frequency clock signal, and a second divider divides the middle frequency clock signal to generate a low frequency reference clock signal. A second phase locked loop receives the low frequency reference clock signal and generates an output signal, compares the output signal to the low frequency reference clock signal to generate a frequency increasing (UP) signal that indicates a phase difference between the output signal and the low frequency reference clock signal. A delay locked loop receives the middle frequency clock signal and the frequency increasing (UP) signal and delays the middle frequency clock signal based on the frequency increasing (UP) signal to generate the realignment clock signal. The second phase lock loop receives the realignment clock signal and adjusts the phase difference between the output signal and the low frequency reference clock signal based on the realignment clock signal.

An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.