A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer stores the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit receives the clock signal from the clock buffer, adjusts a duty cycle of the clock signal to substantially equal to 50%, performs phase interpolation on the clock signal, and provides the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.

A semiconductor circuitry includes an oscillator configured to output an oscillation signal whose frequency depends on a first input signal, a counter configured to count a number of cycles of the oscillation signal, first circuitry configured to output a first digital signal based on a first number of cycles counted by the counter within one of a clock cycle of a clock signal, wherein the first input signal is digitally converted into the first digital signal, and a second circuitry configured to output a second digital signal based on a second number of cycles counted by the counter in a period from a reference timing of the clock signal to an input timing of a second input signal within the one of the clock cycle of the clock signal, wherein the period is digitally converted into the second digital signal.

A clock generating circuit includes a first delay line, a second delay line, a selected phase mixing circuit and, a delay control circuit. The first delay line delays, based on a delay control signal, an input clock signal to generate a first delay clock signal. The second delay line delays, based on the delay control signal, the input clock signal to generate a second delay clock signal. The selected phase mixing circuit generates, based on a first selection signal and a second selection signal, an output clock signal from at least one between the first delay clock signal and the second delay clock signal. The delay control circuit monitors duty cycles of the first delay clock signal and the second delay clock signal to generate the first selection signal and the second selection signal thereby selecting at least one between the first delay line and the second delay line.

Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.

The application provides a calibration method, a calibration device and a multi-phase clock circuit. The method includes: gating each of multi-phase clock signals as a first primary clock signal and gating a corresponding clock signal as a first auxiliary clock signal according to a first preset rule; gating each of the multi-phase clock signals as a second primary clock signal and gating a corresponding clock signal as a second auxiliary clock signal according to a second preset rule; obtaining a time difference between each primary clock signal and its corresponding auxiliary clock signal under the first preset rule and the second preset rule; determining a delay adjustment amount of each primary clock signal according to the time difference, and obtaining a phase error between the multi-phase clock signals according to the delay adjustment amount; and obtaining a calibration amount of the multi-phase clock signals according to the phase error.

A method includes following operations: a delay line delaying a first clock signal by a delay time to generate an output signal; a controller delaying the output signal by a first time interval to generate a first signal; the controller delaying the first clock signal by a second time interval shorter than the first time interval to generate a second clock signal; and the controller controlling the delay line according to the first signal and the second clock signal to adjust the delay time. A delay locked loop device is also disclosed herein.

A semiconductor apparatus includes a memory controller and data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output apparatus configure to output read data from the memory cell array by sensing a logic level of the read data during a low-level period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low-level period of a second clock, the second clock having a set to phase delay amount from the divided clock.

A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer stores the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit receives the clock signal from the clock buffer, adjusts a duty cycle of the clock signal to substantially equal to 50%, performs phase interpolation on the clock signal, and provides the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.