A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.

Described herein is a phase frequency detector (PFD) with a wide operational range. The PFD includes a first flip-flop to receive a reference clock and generate a first output signal based on differences between the reference clock and a feedback clock, a second flip-flop to receive the feedback clock and generate a second output signal based on differences between the reference the feedback clocks, a reset processing path connected to the first flip-flop and second flip-flop, the reset processing path having a reset delay to control a pulse width of a reset signal associated with the first flip-flop and second flip-flop, and an output processing path connected to the first flip-flop and second flip-flop, the output processing path having an output delay to control a pulse width of the first output signal and the second output signal, where the reset processing path and the output processing path are delay independent.

Described herein is a phase frequency detector (PFD) with a wide operational range. The PFD includes a first flip-flop to receive a reference clock and generate a first output signal based on differences between the reference clock and a feedback clock, a second flip-flop to receive the feedback clock and generate a second output signal based on differences between the reference the feedback clocks, a reset processing path connected to the first flip-flop and second flip-flop, the reset processing path having a reset delay to control a pulse width of a reset signal associated with the first flip-flop and second flip-flop, and an output processing path connected to the first flip-flop and second flip-flop, the output processing path having an output delay to control a pulse width of the first output signal and the second output signal, where the reset processing path and the output processing path are delay independent.

Systems and methods are provided for a cascade phase locked loop. A first phase locked loop receives a reference clock signal having a first frequency and generates a high frequency clock signal that is phase aligned with the reference clock signal. A first divider divides the high frequency clock signal to generate a middle frequency clock signal, and a second divider divides the middle frequency clock signal to generate a low frequency reference clock signal. A second phase locked loop receives the low frequency reference clock signal and generates an output signal, compares the output signal to the low frequency reference clock signal to generate a frequency increasing (UP) signal that indicates a phase difference between the output signal and the low frequency reference clock signal. A delay locked loop receives the middle frequency clock signal and the frequency increasing (UP) signal and delays the middle frequency clock signal based on the frequency increasing (UP) signal to generate the realignment clock signal. The second phase lock loop receives the realignment clock signal and adjusts the phase difference between the output signal and the low frequency reference clock signal based on the realignment clock signal.

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.

Apparatus and methods for multiphase clock generation are provided herein. In certain embodiments, a multiphase clock generator includes a first clock buffer that generates a first output clock signal based on a first input clock signal, a second clock buffer that generates a second output clock signal based on a second input clock signal, and a first clock interpolation circuit that generates a third output clock signal based on interpolating the first input clock signal and the second input clock signal. The first clock interpolation circuit generates the third output clock signal based on multiplying the first input clock signal by a first adjustable current to generate a first multiplied current, multiplying the second input clock signal by a second adjustable current to generate a second multiplied current, combining the first multiplied current and the second multiplied current to generate a combined current, and integrating the combined current.