A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.

An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

According to an exemplary embodiment of the present disclosure, a fractional-N sub-sampling phase locked loop using a phase rotator includes a frequency locked loop which is locked at a fractional-N frequency using a delta-signal modulator and a sub-sampling phase locked loop which locks a phase to a fractional multiple using a phase rotator, and the phase rotator applies a fractional multiple to a phase of a signal output from the oscillator.

According to an exemplary embodiment of the present disclosure, a fractional-N sub-sampling phase locked loop using a phase rotator includes a frequency locked loop which is locked at a fractional-N frequency using a delta-signal modulator and a sub-sampling phase locked loop which locks a phase to a fractional multiple using a phase rotator, and the phase rotator applies a fractional multiple to a phase of a signal output from the oscillator.

A clock and data recovery (CDR) system includes a correlator configured to receive data, determine a first value of the received data, and output a second value corresponding to the received data, an accumulator configured to generate an accumulation value by accumulating the second value output from the correlator and output the accumulation value, and a state machine configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value.

One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.