The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

A digital phase-locked loop (DPLL) includes a time-to-digital converter (TDC) to generate a multi-bit code based on a phase error between a reference clock and a feedback clock, a digital loop filter (DLF) coupled to the TDC, a digitally-controlled oscillator (DCO) circuit coupled to the DLF and to generate an output signal that is convertible to the feedback clock, and a logic component coupled to an input of the DCO circuit. The logic component is to: trigger, in response to detecting a power on of the DPLL circuit, a switch to decouple the DLF from the DCO circuit; determine, from the reference clock, a target frequency; measure a frequency of the feedback clock; and iteratively generate, based on the frequency during each iteration, a set of digital bits to the input of the DCO circuit that successively causes the frequency to converge towards the target frequency.

In some examples, a digital frequency locked loop (DFLL) device includes a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal and to determine differences between periods of the reference clock signal and the indicator. The DFLL also includes a controller coupled to the PFD. The controller is configured to store digital signals indicating a first and a second of the differences determined by the PFD, determine a period error by subtracting the second difference from the first difference, and compare the period error to a programmed threshold. The DFLL also includes a digitally controlled oscillator (DCO) coupled to the controller, the DCO configured to provide the primary clock signal having a frequency adjusted based on the comparison.

A time-to-digital converter (TDC) includes a count logic and a digital core. The count logic generates a first sequence of counts representing a first sequence of edges of a first periodic signal, and a second sequence of counts representing a second sequence of edges of a second periodic signal. The digital core generates a sequence of outputs representing the phase differences between the first periodic signal and the second periodic signal from the first sequence of counts and the second sequence of counts. Each output is generated from a pair of successive edges of the first direction of one of the periodic signals and an individual one of the other periodic signal occurring between the pair, and the output is set equal to the minimum of difference of the individual one with the first value of the pair and the individual one with the second value of the pair.

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

A time-to-digital converter includes a delay unit into which a first signal is input and a sampling unit into which a second signal is input. The delay unit includes a first delay chain, a second delay chain, and a third delay chain that are connected in series in sequence. The delay unit delays the first signal. The first delay chain includes at least one first delayer. The second delay chain includes at least three second delayers. The third delay chain includes a third delayer. The delay duration of the first delayer and the delay duration of the third delayer are greater than delay duration of the second delayer. The sampling unit samples output signals of first delayers in the first delay chain, second delayers in the second delay chain, and third delayers in the third delay chain at a preset time point of the second signal.

A time-to-digital converter includes a delay unit into which a first signal is input and a sampling unit into which a second signal is input. The delay unit includes a first delay chain, a second delay chain, and a third delay chain that are connected in series in sequence. The delay unit delays the first signal. The first delay chain includes at least one first delayer. The second delay chain includes at least three second delayers. The third delay chain includes a third delayer. The delay duration of the first delayer and the delay duration of the third delayer are greater than delay duration of the second delayer. The sampling unit samples output signals of first delayers in the first delay chain, second delayers in the second delay chain, and third delayers in the third delay chain at a preset time point of the second signal.

An interpolator includes a first delay circuit, a second delay circuit, and a tunable delay circuit. The first delay circuit delays a first input signal for a fixed delay time, so as generate a first output signal. The second delay circuit delays a second input signal for the fixed delay time, so as to generate a second output signal. The tunable delay circuit delays the first input signal for a tunable delay time, so as to generate an output interpolation signal. The tunable delay time is determined according to the first output signal, the second output signal, and the output interpolation signal.