Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Disclosed is a tuner device including an input terminal, a separator, a first amplifier, a second amplifier, and a tuner. The input terminal receives an input of a reception signal of satellite digital broadcasts. The separator is connected to the input terminal and adapted to frequency-separate a first signal and a second signal. The first signal is in a low-frequency domain of the reception signal, and the second signal is in a high-frequency domain of the reception signal. The first and second amplifiers respectively amplify the first and second signals. The tuner receives an input of output signals from the first and second amplifiers.

A system and method for measuring power supply variations are described. A functional unit includes one or more power supply monitors capable of measuring power supply variations. The power supply monitors forego use of a clock signal from clock generating circuitry and forego use of a reference voltage from a reference power supply. The power supply monitors use an output of a source ring oscillator as a clock signal for the sequential elements of a counter. The counter measures a number of revolutions of a measuring ring oscillator within a period of the output of the source oscillator. The revolutions of the measuring ring oscillator are associated with a number of rising edges and falling edges of the output signal of the measuring ring oscillator. An encoder converts the output of the sequential elements to a binary value, and sends the binary value to an external age tracking unit.

An electronic circuit includes an adaptive delay circuit and a test circuit. The adaptive delay circuit is configured to receive an input clock signal, to further receive a delay setting that specifies first and second delays, and to generate first and second delayed versions of the input clock signal that are delayed relative to the input clock signal by the first and second delays, respectively. The test circuit is configured to test the adaptive delay circuit by (i) programming the adaptive delay circuit with multiple different delay settings that each specifies a respective first delay and a respective second delay, (ii) for each of the multiple delay settings, measuring an actual time offset between the first and second delayed versions of the input clock signal, and (iii) generating a test result based on actual time offsets measured for the multiple different delay settings.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

A system for generating an RFPWM signal comprises a delta sigma modulator having a plurality of outputs, a phase-locked loop comprising a plurality of phase quantization outputs, at least one multiplexer having a plurality of signal inputs, a plurality of selector inputs, and at least one output, the signal inputs communicatively connected to the phase quantization outputs of the phase-locked loop and the selector inputs electrically connected to the outputs of the delta sigma modulator, and a driver having an input communicatively connected to the output of the multiplexer and an output generating an RFPWM signal. A method of generating an RFPWM signal is also described.

An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.

A time synchronization device adapted for an electronic apparatus, an electronic apparatus, a time synchronization system and a time synchronization method. The time synchronization device includes: a signal generating circuit and a time adjusting circuit. The signal generating circuit includes: a control circuit, configured to generate a frequency control word; and a signal adjusting circuit, configured to receive the frequency control word and an input signal having an initial frequency, and to generate and output an output signal having a target frequency based on the frequency control word and the input signal. The time adjusting circuit is configured to perform a synchronization adjusting operation on a clock signal of the electronic apparatus based on the output signal having the target frequency.