The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.

An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

Some examples relate to a frequency synthesizer. The frequency synthesizer includes an oscillator including an input terminal and an output terminal. A frequency locked-loop or phase-locked loop (FLL/PLL) unit is arranged on a feedback path extending between the output terminal of the oscillator and the input terminal of the oscillator. A switching unit is configured to selectively switch between a first mode of operation in which the feedback path is closed and the FLL/PLL unit is coupled to the input terminal of the oscillator, and a second mode of operation in which the feedback path is open and a ramping unit is coupled to the input terminal of the oscillator while the feedback path is open.

An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

The present invention relates to a frequency modulation method based on a phase-locked loop capable of performing fast modulation independent of bandwidth. A frequency modulation system based on a phase-locked loop capable of performing fast modulation independent of bandwidth according to the present invention includes a loop filter including a proportional path and an integral path to determine a bandwidth of a phase-locked loop, a voltage-controlled oscillator configured to adjust a frequency according to an output of the loop filter, and a slope alternator configured to alternate an input current of the loop filter, wherein the slope alternator is located in the integral path of the loop filter to generate an offset current at a moment of change from a modulation rise to a modulation fall.

A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

A frequency synthesizer with microcode control that allows one or more programmable circuits of a frequency synthesizer system to be programmed using a plurality of microcode instructions. A method includes, setting a frequency synthesizer system to operate in a microcode mode, programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions and executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system.

A method for generating a clock signal using a digital phase-locked loop includes updating a gain of a variable gain digital filter of the digital phase-locked loop using an estimate error of a current estimate of a phase and a frequency of an input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The method may include calculating the current estimate of the phase and the frequency of the input clock signal based on a previous estimate of the phase and the frequency of the input clock signal, the measurement of the phase and the frequency of the input clock signal, and the gain of the variable gain digital filter. The gain may be updated every cycle of the input clock signal.