In an embodiment, a method includes initializing an input clock rotating register by sending a reset signal synchronized to an input clock signal and initializing an output clock rotating register by sending the reset signal synchronized to an output clock signal. The method further providing a data input synchronized to the output clock to a plurality of mux-flops. The output clock rotating register activates one of the plurality of mux-flops to receive the data input. The method further includes forwarding the data input via the one of the plurality of mux-flops to a multiplexer. The multiplexer has a selection input of the input clock rotating register. The method further includes selecting the data input as the output of the multiplexer to be a data output signal, such that the data output is synchronized with the input clock.

In one embodiment, a phase lock loop circuit includes a control circuit, wherein the control circuit is configured to input an estimation having a second frequency and a second phase. The second frequency is selected from a range of frequencies including a first frequency from an acquired signal. A numerically controlled oscillator is coupled to the control circuit, wherein the control circuit is configured to control an output response of the numerically controlled oscillator. The numerically controlled oscillator is configured to receive the estimation from the control circuit and generate an output signal in response to the estimation. A phase detector is coupled to the control circuit and the numerically controlled oscillator, wherein the phase detector is configured to compare the first signal and the output signal and produce a comparison output, the comparison output indicative of a phase difference between the first signal and the estimation.

The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.

In one embodiment, a phase lock loop circuit includes a control circuit, wherein the control circuit is configured to input an estimation having a second frequency and a second phase. The second frequency is selected from a range of frequencies including a first frequency from an acquired signal. A numerically controlled oscillator is coupled to the control circuit, wherein the control circuit is configured to control an output response of the numerically controlled oscillator. The numerically controlled oscillator is configured to receive the estimation from the control circuit and generate an output signal in response to the estimation. A phase detector is coupled to the control circuit and the numerically controlled oscillator, wherein the phase detector is configured to compare the first signal and the output signal and produce a comparison output, the comparison output indicative of a phase difference between the first signal and the estimation.

The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.

A self-start-up control circuit adaptable to an oscillation circuit includes a state circuit that generates a reset signal according to a level of a control voltage for a voltage-controlled oscillator (VCO) of the oscillation circuit; and a start-up circuit that starts up the VCO by generating an enable signal according to the reset signal.

A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

The disclosure discloses a coarse adjustment cell array applied to a digitally controlled oscillator and a related apparatus. The coarse adjustment cell array applied to the digitally controlled oscillator includes X coarse adjustment cells, and each coarse adjustment cell in the coarse adjustment cell array includes a logic cell and W fine adjustment cells; and input to a logic cell of a coarse adjustment cell i in the coarse adjustment cell array includes Y coarse adjustment control bits and W fine adjustment control bits, output from the logic cell of the coarse adjustment cell i is used to control whether W fine adjustment cells in the coarse adjustment cell i work, Y is an integer greater than 1, and X and W are integers greater than 1.

A method can be used for managing the operation of a phase-locked loop. The loop includes an oscillator voltage controlled by a control signal and a phase comparator receiving a reference signal and a feedback signal which arises from the output signal of the oscillator. The method includes a detection of a possible absence of transitions on the feedback signal for a first duration and, in response to such an absence, a forcing of the lowering of the voltage of the control signal at least until a reappearance of transitions on the feedback signal.

A method can be used for managing the operation of a phase-locked loop. The loop includes an oscillator voltage controlled by a control signal and a phase comparator receiving a reference signal and a feedback signal which arises from the output signal of the oscillator. The method includes a detection of a possible absence of transitions on the feedback signal for a first duration and, in response to such an absence, a forcing of the lowering of the voltage of the control signal at least until a reappearance of transitions on the feedback signal.