An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.

In one embodiment, a phase lock loop circuit includes a control circuit, wherein the control circuit is configured to input an estimation having a second frequency and a second phase. The second frequency is selected from a range of frequencies including a first frequency from an acquired signal. A numerically controlled oscillator is coupled to the control circuit, wherein the control circuit is configured to control an output response of the numerically controlled oscillator. The numerically controlled oscillator is configured to receive the estimation from the control circuit and generate an output signal in response to the estimation. A phase detector is coupled to the control circuit and the numerically controlled oscillator, wherein the phase detector is configured to compare the first signal and the output signal and produce a comparison output, the comparison output indicative of a phase difference between the first signal and the estimation.

A signal generator includes a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a ramping signal based on the first reference signal, where the ramping signal is between a minimum frequency and a maximum frequency of a radar frequency band; a system clock configured to generate a second reference signal having a common system reference frequency; and a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.

The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.

The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.

Example implementations relate to partitioning a radio into chains to scan channels. In some examples, a network device may comprise a processing resource and a memory resource storing machine-readable instructions to partition a default radio of the network device into a service chain and a scan chain in response to a scan request, scan a particular channel with the scan chain to discover devices operating on the particular channel of a network, and combine the service chain and the scan chain into the default radio.

Example implementations relate to partitioning a radio into chains to scan channels. In some examples, a network device may comprise a processing resource and a memory resource storing machine-readable instructions to partition a default radio of the network device into a service chain and a scan chain in response to a scan request, scan a particular channel with the scan chain to discover devices operating on the particular channel of a network, and combine the service chain and the scan chain into the default radio.

A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

An imaging apparatus allows a clock data recovery device to reestablish reception of data even when the clock data recovery device has failed to lock a phase. A reception unit includes a locking unit configured to perform a locking operation for receiving the data and a detection unit configured to detect a lock state of the locking unit. A control unit controls performing of the locking operation again by the locking unit in a case where a lock is not achieved, based on a detection result detected by the detection unit.

An imaging apparatus allows a clock data recovery device to reestablish reception of data even when the clock data recovery device has failed to lock a phase. A reception unit includes a locking unit configured to perform a locking operation for receiving the data and a detection unit configured to detect a lock state of the locking unit. A control unit controls performing of the locking operation again by the locking unit in a case where a lock is not achieved, based on a detection result detected by the detection unit.