A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.

A steady-state voltage on an oscillator output can be detected, independent of control signals received from other circuitry, by an oscillator failure detection circuit (OFDC) fabricated within an integrated circuit (IC). The OFDC can, in response to detecting the steady-state voltage, output an oscillator failure signal on a reference fail output. The OFDC can receive, with a first and a second buffer, an oscillator output signal from an oscillator output. Through the use of an electrically interconnected, pull-down device, pull-up network, pull-up device, pull-down network, Schmitt trigger, inverting Schmitt trigger and OR-gate, the OFDC can drive the oscillator failure signal onto an output of the OR-gate electrically connected to a reference fail output (RFO).

A system and a method for hitless clock switching are provided. In the system, a sampling circuitry group samples a primary reference clock signal and a secondary reference clock signal to obtain first and second sampling information, respectively. A phase detector group obtains a phase difference between the primary and secondary reference clock signals with the first and second sampling information. A compensator group adds the phase difference to a phase of the secondary reference clock signal to obtain a backup reference clock signal. When the primary reference clock signal is abnormal or missing, the signal selector determines the backup reference clock signal as a target reference clock signal and sends it to a phase-locked loop. The phase-locked loop performs loop control on the target reference clock signal, thereby implementing hitless switching of reference clock signals.

A clock recovery circuit includes a multi-phase sampling circuit, a phase comparison circuit, a recovery clock generation circuit, and a phase shifter. The multi-phase sampling circuit includes edge samplers and data samplers. A data signal is input to each of the edge samplers and each of the data samplers. The phase comparison circuit is disposed at an output side of the multi-phase sampling circuit. The recovery clock generation circuit is configured to output multi-phase clock signals. The phase shifter is disposed between the recovery clock generation circuit and the multi-phase sampling circuit and configured to generate a plurality of clock signals to be supplied to the multi-phase sampling circuit by shifting a phase of a first one of the multi-phase clock signals output from the recovery clock generation circuit by a shift amount different from a shift amount of a second one of the multi-phase clock signals.

A clock recovery circuit includes a multi-phase sampling circuit, a phase comparison circuit, a recovery clock generation circuit, and a phase shifter. The multi-phase sampling circuit includes edge samplers and data samplers. A data signal is input to each of the edge samplers and each of the data samplers. The phase comparison circuit is disposed at an output side of the multi-phase sampling circuit. The recovery clock generation circuit is configured to output multi-phase clock signals. The phase shifter is disposed between the recovery clock generation circuit and the multi-phase sampling circuit and configured to generate a plurality of clock signals to be supplied to the multi-phase sampling circuit by shifting a phase of a first one of the multi-phase clock signals output from the recovery clock generation circuit by a shift amount different from a shift amount of a second one of the multi-phase clock signals.

A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.

Limiting frequency overshoot in a timing recovery loop involves using a proportional-integral (PI) control system to discipline a frequency of an output signal of a voltage controlled oscillator (VCO) in accordance with a time reference signal. A control signal output of the PI control system is monitored to detect conditions which will prospectively cause an excess deviation of the VCO frequency. In response to detecting such a condition, an output of an integral error term generator of the PI control system is locked or held constant. This will have the effect of preventing the excess frequency deviation of the VCO.

A PLL uses a virtual clock signal during holdover and/or startup to maintain a closed loop for the PLL and allow for phase/frequency adjustment of the PLL output through the feedback divider during holdover/startup when reference clock(s) supplied to the PLL are unavailable. The virtual clock signal is a series of digital values separated by a time period, where the digital values indicate transitions of the virtual clock signal and the time period corresponds to a period of the virtual clock signal. A selector circuit selects as a digital reference clock signal the virtual clock signal in a holdover or startup mode and another reference clock signal in normal operation.

A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.

Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.