A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

An asynchronous circuit portion for sampling an input signal is provided. The circuit portion comprises a sampling circuit portion arranged to sample the input signal to generate a sanitized output signal corresponding to the input signal; a comparison circuit portion arranged to compare the sanitized output signal with the input signal and to generate a change signal if the sanitized output signal does not correspond to the input signal; and a control circuit portion arranged to trigger the sampling circuit portion to sample the input signal to generate an updated sanitized output signal, in response to the change signal.

An asynchronous circuit portion for sampling an input signal is provided. The circuit portion comprises a sampling circuit portion arranged to sample the input signal to generate a sanitized output signal corresponding to the input signal; a comparison circuit portion arranged to compare the sanitized output signal with the input signal and to generate a change signal if the sanitized output signal does not correspond to the input signal; and a control circuit portion arranged to trigger the sampling circuit portion to sample the input signal to generate an updated sanitized output signal, in response to the change signal.

A phase locked loop includes a pulse limiter between a phase frequency detector and a charge pump. The phase frequency detector generates and sends a clock pulse to the pulse limiter. The pulse limiter generates a first signal that indicates that the clock pulse is greater than a minimum pulse width of the phase frequency detector. The pulse limiter receives a pulse limiter buffer selection signal that selects one buffer of a plurality of buffers within the pulse limiter. The pulse limiter generates a second signal that indicates a truncated pulse width as the minimum pulse width of the phase frequency detector plus a delay period that is associated with the pulse limiter buffer selection signal. The pulse limiter truncates the clock pulse to the truncated pulse width and sends the truncated clock pulse to the charge pump.

An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

A test and measurement instrument includes a first data channel including a first data converter operating at a first rate, and a second data channel including a second data converter operating at a second rate that is different than the first rate. Rate controls may include a clock generation circuit. The clock generation circuit includes an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, and a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock. The first frequency clock may be used to control the rate of the first data channel, and the second frequency clock may be used to control the rate of the second data channel. Methods are also described.

A method for timing aperture synthesis arrays comprising the steps of: (a) coupling a plurality of independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency; (b) digitally synchronizing the plurality of independent crystal oscillators in phase; (c) combining the unique output frequencies; and (d) obtaining a stable digital reference signal for timing at least one remote radio device of the aperture synthesis array.

A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.

An apparatus includes a digitally controlled oscillator (DCO), which includes an inductor coupled in series with a first capacitor. The DCO further includes a second capacitor coupled in parallel with the series-coupled inductor and first capacitor, a first inverter coupled in parallel with the second capacitor, and a second inverter coupled back-to-back to the first inverter. The DCO further includes a digital-to-analog-converter (DAC) to vary a capacitance of the first capacitor.