Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

A phase locked loop circuit that is capable of stabilizing a frequency of an input signal even in the case where the frequency is unstable is provided. The phase locked loop circuit 12 that corrects a frequency error of an output signal from an oscillator to a predetermined target frequency; an ADC 121 that converts the output signal to a digital signal; reference frequency output means 123 that outputs a reference frequency signal; frequency error detection means 122a that detects the frequency error based on the digital signal and the reference frequency signal; correction signal generation means 122b that generates an error correction signal based on the frequency error; a DAC 124 that converts the error correction signal to an analog signal; and a multiplier 125 that multiplies the output signal by the analog signal to correct the frequency error of the output signal.

An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method or autonomous vehicle is also disclosed.

An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method or autonomous vehicle is also disclosed.

Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

The present disclosure relates to tuning oscillatory systems. The teachings thereof may be embodied in a device having an adjustable capacitance value for tuning a first oscillatory system, connectable to a second oscillatory system having an unknown and weak coupling factor. The device may include: a first capacitor having a capacitance dependent upon a voltage; and a DC voltage source having a variable voltage applied to associated terminals; a series-connected arrangement of the DC voltage source and a decoupling element connected in parallel with terminals of the capacitor, to apply a variable bias voltage to the first capacitor. The voltage applied to the terminals of the DC voltage source may depend at least in part on a working frequency of the first oscillatory system.

An object detection system in a surrounding environment of a vehicle. The detection system comprising, a radar, and a processing unit. The radar comprising a transmitter, a receiver, and an ultra-low phase-noise frequency synthesizer. The detection system gathers electromagnetic data of the objects from radio signal received by the receiver; classify each of the objects by analyzing the gathered electromagnetic data; continuously compare classifications and object detections to immediate past classifications and object detections, and to previously classified and detected objects; continuously validate current, immediate past, and past object detections; generate a three-dimensional electromagnetic-map of the surrounding environment by utilizing the electromagnetic signatures of each of the classified objects; and reclassify objects and combine the generated three-dimensional electromagnetic map with one of a geographical-map, a physical map, or a combination thereof to determine a direction and a distance of each of the one or more classified objects from the system.

The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.