An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method or autonomous vehicle is also disclosed.

An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method or autonomous vehicle is also disclosed.

The system includes an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal, and a sub-sampling PLL (SSPLL) that generates a high-frequency output signal based on an input. A switch selects either the reference signal or the IF signal to be the input to the SSPLL. When the reference signal is the input to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode, and when the IF signal is the input to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode. A sub-sampling lock detector (SSLD) determines whether the frequency synthesizer becomes unlocked during the normal-operating mode, and if so, activates the switch to move the system into the frequency-acquisition mode. It also determines whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activates the switch to move the system into the normal-operating mode.

The system includes an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal, and a sub-sampling PLL (SSPLL) that generates a high-frequency output signal based on an input. A switch selects either the reference signal or the IF signal to be the input to the SSPLL. When the reference signal is the input to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode, and when the IF signal is the input to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode. A sub-sampling lock detector (SSLD) determines whether the frequency synthesizer becomes unlocked during the normal-operating mode, and if so, activates the switch to move the system into the frequency-acquisition mode. It also determines whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activates the switch to move the system into the normal-operating mode.

The system includes an intermediate-frequency (IF) synthesizer that generates an IF signal based on a reference signal, and a sub-sampling PLL (SSPLL) that generates a high-frequency output signal based on an input. A switch selects either the reference signal or the IF signal to be the input to the SSPLL. When the reference signal is the input to the SSPLL, the frequency synthesizer operates in a low-noise normal-operating mode, and when the IF signal is the input to the SSPLL, the frequency synthesizer operates in a higher-noise, frequency-acquisition mode. A sub-sampling lock detector (SSLD) determines whether the frequency synthesizer becomes unlocked during the normal-operating mode, and if so, activates the switch to move the system into the frequency-acquisition mode. It also determines whether the frequency synthesizer becomes relocked to the target frequency during the frequency-acquisition mode, and if so, activates the switch to move the system into the normal-operating mode.

Apparatus and methods demonstrate a chip-scale direct optical to RF link that frequency divides up to 120 GHz optical frequency combs to 10 GHz using harmonic multi-tone injection locking. The embodied invention links widely separated optical frequency combs in the millimeter wave regime (>120 GHz) or THz domain (100s of GHz to THz domain), e.g., microresonator-based frequency combs, which are currently outside of the photo-detection region, into the microwave domain (10s of GHz) where it can be easily photo-detected and controlled. The technique works as a perfect optical divider, using a mode-locked laser and optical injection locking as the technique to phase-lock both lasers.

Apparatus and methods demonstrate a chip-scale direct optical to RF link that frequency divides up to 120 GHz optical frequency combs to 10 GHz using harmonic multi-tone injection locking. The embodied invention links widely separated optical frequency combs in the millimeter wave regime (>120 GHz) or THz domain (100s of GHz to THz domain), e.g., microresonator-based frequency combs, which are currently outside of the photo-detection region, into the microwave domain (10s of GHz) where it can be easily photo-detected and controlled. The technique works as a perfect optical divider, using a mode-locked laser and optical injection locking as the technique to phase-lock both lasers.

Apparatus and methods demonstrate a chip-scale direct optical to RF link that frequency divides up to 120 GHz optical frequency combs to 10 GHz using harmonic multi-tone injection locking. The embodied invention links widely separated optical frequency combs in the millimeter wave regime (>120 GHz) or THz domain (100s of GHz to THz domain), e.g., microresonator-based frequency combs, which are currently outside of the photo-detection region, into the microwave domain (10s of GHz) where it can be easily photo-detected and controlled. The technique works as a perfect optical divider, using a mode-locked laser and optical injection locking as the technique to phase-lock both lasers.

Apparatus and methods demonstrate a chip-scale direct optical to RF link that frequency divides up to 120 GHz optical frequency combs to 10 GHz using harmonic multi-tone injection locking. The embodied invention links widely separated optical frequency combs in the millimeter wave regime (>120 GHz) or THz domain (100s of GHz to THz domain), e.g., microresonator-based frequency combs, which are currently outside of the photo-detection region, into the microwave domain (10s of GHz) where it can be easily photo-detected and controlled. The technique works as a perfect optical divider, using a mode-locked laser and optical injection locking as the technique to phase-lock both lasers.

A frequency synthesis device with high multiplication rank, including a base frequency generator generating two first base signals of square shape of same frequency and opposite to each other, a first synthesis stage including two first switching power supply oscillators, of which the power supplies are respectively switched by the two first base signals, a second synthesis stage including a second switching power supply oscillator of which the supply is switched by a combination of the output signals of the two first oscillators, the output of the second switching power supply oscillator being filtered by a frequency discriminator circuit realized with an injection locked oscillator.