A SAR ADC (50) is disclosed. It comprises a differential input port having a first input (V.sub.inP) configured to receive a first input voltage and a second input (V.sub.inN) configured to receive a second input voltage, of opposite polarity compared with first input voltage. Furthermore, it comprises a (300) having a first sub circuit (310P) comprising a first plurality of capacitors (2C.sub.u, C.sub.u), each connected to a common node (320P) of the first sub circuit (310P) with a first terminal, and a second sub circuit (310N) comprising a second plurality of capacitors (2C.sub.u, C.sub.u), each connected to a common node (320N) of the second sub circuit (310N) with a first terminal. For each capacitor (2C.sub.u, C.sub.u) of the first plurality of capacitors, the first sub circuit (310P) comprises a first switch (S4) connected between the first input (V.sub.inP) of the SAR ADC and a second terminal of that capacitor, a second switch (S.sub.2) connected between a first reference-voltage input (V.sub.rP) and the second terminal of that capacitor, a third switch (S.sub.1) connected between a second reference-voltage input (V.sub.rN) and the second terminal of that capacitor, and a capacitive device (X.sub.P) connected between the second input (V.sub.inN) of the SAR ADC and the second terminal of that capacitor. The second sub circuit is arranged in a similar way.

A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

A method for operating an input device, the method involving obtaining a number of non-sinusoidal transmitter signals with unique base frequencies, and selecting a sampling frequency of an analog-to-digital converter (ADC) such that a number of aliasing artifacts associated with higher harmonics of the non-sinusoidal transmitter signals is located at frequencies different from the base frequencies.

The present invention provides a receiving circuit, wherein the receiving circuit includes a first ADC, an attenuator, a second ADC, a harmonic generation circuit and an output circuit. In the operations of the receiving circuit, the first ADC performs an analog-to-digital operation on an analog input signal to generate a first digital output signal, the attenuator reduces strength of the analog input signal to generate an attenuated analog input signal, the second ADC performs the analog-to-digital operation on the attenuated analog input signal to generate a second digital input signal, the harmonic generation circuit generates at least one harmonic signal according to the second digital input signal, and the output circuit deletes a harmonic component of the first digital input signal by using the at least one harmonic signal to generate an output signal.

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

An apparatus configured to transmit and receive a radio frequency (RF) signal is provided. The apparatus includes a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal, a power amplifier configured to amplify the analog signal, and an antenna configured to output, as the RF signal, the amplified analog signal to the outside. The DAC includes a current cell matrix including a plurality of current cells configured to generate the analog signal, a plurality of normal paths configured to control the plurality of current cells to be turned on or off, based on the digital signal, and a plurality of alternative paths configured to selectively consume power, based on a pattern of the digital signal.

An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.

A device for processing digital signals is provided. The device comprises a digital signal source and a converter circuit having a current supply. The digital signal source outputs a codeword. The converter circuit receives the codeword from the digital signal source, receives a current at the current supply, and generates an output signal based on the codeword. The current is generated in accordance with the codeword.