The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.

A receiver circuit for an antenna array system (AAS) is disclosed. The receiver circuit (10) comprises a set of receivers (15.sub.1-15.sub.p). Each receiver (15.sub.1-15.sub.p) comprises a first TI-ADC (35.sub.1) in a receive path of the receiver. The first TI-ADC (35.sub.1) comprises a plurality of sub ADCs (A.sub.1-A.sub.M+N). Each receiver (15.sub.1-15.sub.p) comprises a control circuit (40) configured to select which sub ADC (A.sub.1-A.sub.M+N) is to operate on what input sample based on a first selection sequence. The control circuits (40) in the different receivers (15.sub.1-15.sub.p) in said set of receivers (15.sub.1-15.sub.p) are configured to use different first selection sequences.

A digital to analog converter for fiber optic gyroscope is disclosed. The digital to analog converter for fiber optic gyroscope includes a random unit generating a random number signal, a plurality of encoding units coupled with the random unit, a plurality of control units respectively one to one coupled with the plurality of encoding units, a current source array coupled with the plurality of control units, and an output load electrically connected to the current source array. Each of the plurality of encoding units converts a plurality of digital signals to a plurality of spin signals according to the random number signal. Each of the plurality of control units converts the plurality of spin signals to a plurality of logic signals. The current source array generates a total current according to the plurality of logic signals. The total current passes through the output load and forms an analog signal.

Disclosed are a readout circuit, a signal quantizing method, a signal quantizing device, and a computer device. The readout circuit includes: a signal sampler, including a plurality of channels; a plurality of integrators, connected to the plurality of channels and having a one-to-one releationship with the plurality of channels; a signal processor, including a first operational amplifier, a sampling input of the first operational amplifier being connected to outputs of the plurality of integrators, respectively; and an analog-digital converter. An input of the analog-digital converter is connected to an output of the first operational amplifier.

The present disclosure relates generally to digital microphone and other sensor assemblies including a transducer and a delta-sigma analog-to-digital converter (ADC) with digital-to-analog converter (DAC) element mismatch shaping and more particularly to sensor assemblies and electrical circuits therefor including a dynamic element matching (DELM) entity configured to select DAC elements based on data weighted averaging (DWA) and a randomized non-negative shift.

A TI-ADC (50) comprising a group of sub-ADCs (A.sub.1-A.sub.M+N) is disclosed. During operation, M≥2 of the sub-ADCs (A.sub.1-A.sub.M+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A.sub.1-A.sub.M+N) in the group is M+N, N≥1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A.sub.1-A.sub.M+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A.sub.1-A.sub.M+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (A.sub.k.sub.1) in a first subset of the group of sub-ADCs (A.sub.1-A.sub.M+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme. Moreover, the control N circuit (55) is configured to, for sub-ADCs (A.sub.k.sub.2) in a second subset of the group of sub-ADCs (A.sub.1-A.sub.M+N), which are not subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a second scheme, different from the first scheme.

A time interleaved analog-to-digital converter (TIADC) is provided. The TIADC converts an input signal into a digital output signal and includes N analog-to-digital converters (ADCs), a clock generation circuit, and a control circuit. The N ADCs receive the input signal and sample the input signal according to N sampling clocks to each generate a digital output code, N being an integer greater than or equal to 2. The clock generation circuit is configured to receive a working clock and a set of control values and to generate the N sampling clocks according to the set of control values and the working clock. The control circuit is configured to periodically generate the set of control values based on a pseudo random number and to output the digital output codes in turn as the digital output signal.

A switched-capacitor delta-sigma data converter circuit includes compensation for voltage reference error that may cause non-linearity and inter-channel crosstalk. The circuit includes a voltage reference circuit, an integrator, a quantizer that quantizes the output of the integrator and a reference feedback switched-capacitor network that provides feedback charge quanta to the integrator that represents an output of the quantizer, so that the output of the quantizer, on average, represents an input signal provided to the integrator. In addition, a compensation switched-capacitor network is included for drawing dummy load charge quanta from the voltage reference output that is not provided to the integrator so that a total charge drawn from the voltage reference output when the reference feedback switched-capacitor network is coupled to the voltage reference output does not vary as the input voltage varies.

There is described an analog-to-digital converter, ADC, device (100), comprising: i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13); ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to: swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).

A TI-ADC (50) comprising a group of sub-ADCs (A.sub.1-A.sub.M+N) is disclosed. During operation, M≥2 of the sub-ADCs (A.sub.1-A.sub.M+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A.sub.1-A.sub.M+N) in the group is M+N, N≥1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A.sub.1-A.sub.M+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A.sub.1-A.sub.M+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (A.sub.k.sub.1) in a first subset of the group of sub-ADCs (A.sub.1-A.sub.M+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme. Moreover, the control N circuit (55) is configured to, for sub-ADCs (A.sub.k.sub.2) in a second subset of the group of sub-ADCs (A.sub.1-A.sub.M+N), which are not subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a second scheme, different from the first scheme.