A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

An analog input device, which converts an inputted analog signal to a digital signal and outputs the digital signal, includes a high resolution AD converter, a first low resolution AD converter, and a second low resolution AD converter. When a difference between a first digital signal converted by the high resolution AD converter and a second digital signal converted by the first low resolution AD converter is equal to or less than a predetermined first threshold, the analog input device outputs first digital signal. When the difference between the first digital signal and the second digital signal is larger than the predetermined first threshold, the analog input device stops an output of the first digital signal.

A physical quantity detection circuit includes: a detection signal generation circuit generating a detection signal, based on an output signal from a physical quantity detection element; an analog/digital converter circuit converting the detection signal into a first digital signal and converting a test signal into a second digital signal; a test signal generation circuit generating the test signal; and a malfunction diagnosis circuit diagnosing a malfunction of the analog/digital converter circuit, based on the second digital signal. A full-scale voltage of the analog/digital converter circuit is selected from among a plurality of voltages having different magnitudes, according to a power supply voltage. The test signal includes an upper limit value test signal, a lower limit value test signal, and a first intermediate value test signal. The test signal generation circuit performs resistive voltage division of the full-scale voltage and thus generates the first intermediate value test signal.

Methods are provided for supervising a motor control unit with at least two separate channels, each of the two channels including at least: means for executing a given application task AS, the application task AS including a plurality of successively executed computations between which latency periods elapse; a first component capable of performing the computations; a second component capable of storing data; the application tasks AS of the channels being capable of communicating. The method comprising includes the following steps: a) detecting a latency period; b) performing, during this latency period, an operating state test of at least one of the components; and c) determining a state of the component corresponding to a failure state or a healthy state.

A control system includes: a semiconductor chip, having built therein a processing part, an A/D converter and a pull device circuit; a wiring part, having one end connected to a terminal connected to the A/D converter; and a sensor, connected to the other end of the wiring part and inputting a sensor signal in analog form via the wiring part. The pull device circuit includes a switching element, and has one end connected to ground or a power supply voltage and the other end connected between the A/D converter and the terminal. The processing part includes: a switch control part, controlling the switching element to be in an on or off state; a sensor information generator, generating sensor information based on the sensor signal; and a disconnection detector, detecting disconnection of the wiring part based on output of the A/D converter when the switching element is in the on state.

An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

A sampling clock generating circuit and an analog to digital converter includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; an output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit; and the other end of the resistance variable circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.

In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.

An A/D conversion circuit includes a reference voltage source to generate a calibration voltage, a multiplexer to receive an analog signal and the calibration voltage, and output the analog signal selected in a normal mode and the calibration voltage selected in a calibration mode or a self-diagnosis mode, an A/D converter to convert an output signal from the multiplexer into a digital signal, a non-volatile memory to hold the digital signal and calibration data, a digital calibration part to calibrate the digital signal in case of inputting the analog signal to the A/D converter in the normal mode based on the calibration data, and a self-diagnosis circuit to diagnose the A/D converter based on the digital signal in case of inputting the calibration voltage to the A/D converter in the self-diagnosis mode, and the digital signal stored in the non-volatile memory.

There is disclosed herein analogue-to-digital converter circuitry, comprising a set of sub-ADC units each for carrying out analogue-to-digital conversion operations, the set comprising a given number of core sub-ADC units for carrying out said given number of core conversion operations. Also provided is control circuitry operable, when a said sub-ADC unit is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried by the sub-ADC units of the set sub-ADC units other than the defective sub-ADC unit.