Apparatus includes an ADC configured to convert an analog signal to a digital signal, a comparator having a first input responsive to the analog signal, a second input responsive to the digital signal, and an output at which a comparison signal is provided, and an output checker configured to process the comparison signal to generate a fault signal indicative of whether a fault has occurred in the ADC. The comparator can be an analog comparator in which case the digital signal is converted to an analog signal for the comparison or a digital comparator in which case an additional ADC is provided to convert the analog signal into a digital signal for the comparison. Embodiments include more than one ADC in which case summation elements are provided to sum the analog signals and the digital signals for the comparison.

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

A system may include ADC circuitry. To test the performance of the ADC circuitry, the system may include ADC testing circuitry coupled to the ADC circuitry. In particular, the ADC testing circuitry may include reference voltage generation circuitry configured to generate reference voltages serving as test voltages for the ADC circuitry. The ADC circuitry may be coupled to a test input for receiving the test voltages via switching circuitry and may be coupled to a main data input for receiving system data via the switching circuitry. Testing may occur during an idling time period of the system and when the switching circuitry couples the test input to the ADC circuitry. Test input voltages corresponding to one or more stages in the ADC circuitry may be provided to the ADC circuitry, and corresponding output values from the ADC circuitry may be compared to an expected value and/or expected threshold values.

An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

A calibration circuit, including: a signal generator circuit configured to generate a modulated analog input signal, which is based on a digital input word that is modulated; an Analog-to-Digital Converter (ADC) configured to convert an analog reference signal to a digital calibration word, wherein the analog reference signal is a low-pass-filtered version of the analog input signal generated by the signal generator circuit; and a feedback circuit configured to output the digital input word by adjusting the digital calibration word depending on a digital feedback signal, which is based on a modulated version of the analog reference signal, wherein the signal generator circuit, the ADC, and the feedback circuit are provided on a same chip.

A digital-to-analog converter (DAC) includes a switching network and built-in-self-test (BIST) circuitry. The DAC, in operation, generates analog output signals in response to input codes of a set of input codes of the DAC. The BIST circuitry sequentially applies codes of a determined subset of codes of the set of input codes to test the plurality of switches. The determined subset of codes has fewer codes than the set of input codes. The BIST circuitry detects failures of switches of the plurality of switches based on responses of the DAC to the applied codes. In response to detecting a failure of a switch, the BIST generates a signal indicating a failure of the switching network.

Provided is a method for testing a semiconductor device having an A/D converter, the method includes supplying a sinusoidal analog test signal S1 to an A/D converter, storing a group S2 of output codes generated by the A/D converter over a period with an integer K multiple duration of the cycle of the sine wave, in response to the analog test signal S1, and generating a histogram of the stored group S2 of the output codes, and evaluating the A/D converter on the basis of the histogram.

The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

In accordance with an embodiment, a method for operating an analog-to-digital converter (ADC) includes: determining a trip point of a comparator of the ADC by applying a first signal having a first slope to an input of the ADC, and monitoring an output state of the comparator in response to the first signal; and after applying the first signal, applying a second signal having a second signal level based on the determined trip point of the comparator, monitoring values of an output code of the ADC in response to the second signal, and generating statistical information based on the monitored values of the output code, where the second signal is a static signal or has as second slope less than the first slope.