Provided are a Time-Interleaved Successive Approximation Register Analog-to-Digital Converter, TISAR ADC, and a calibration method thereof. The calibration method for the TISAR ADC may include: sampling an analog signal input into the TISAR ADC to generate a reference digital signal (S130); according to the reference digital signal and output digital signals generated by analog-to-digital conversion sub-modules of the TISAR ADC, obtaining capacitor array calibration parameters and time delay calibration parameters of the analog-to-digital conversion sub-modules; adjusting capacitor arrays of the corresponding analog-to-digital conversion sub-modules according to the capacitor array calibration parameters, respectively; and adjusting time delays of the corresponding analog-to-digital conversion sub-modules according to the time delay calibration parameters, respectively.

A semiconductor integrated circuit includes a converter converting an analog signal into a digital signal based on a clock signal; a comparator determining values of data based on the digital signal; a recovery circuit recovering the clock signal based on the digital signal and the data; and a control circuit. The recovery circuit includes a phase detector calculating a sum of a first value and offset, the first value being a value based on the digital signal and the data and relating to a phase of the clock signal; and a loop filter calculating a correction amount of the phase of the clock signal based on the sum. The control circuit is configured to gradually change the offset from a second value to zero after the second value is added as the offset.

An apparatus and a method of correcting a mismatch of a time-interleaved analog-to-digital converter are provided. The apparatus may include: a time-interleaved analog-to-digital converter configured to receive a non-return-to-zero (NRZ) signal in a correction mode and generate a first output signal, and including a plurality of analog-to-digital converters; and a mismatch corrector configured to generate a second output signal by processing the first output signal of the time-interleaved analog-to-digital converter based on parameters, wherein the parameters may be generated based on the first output signal of the time-interleaved analog-to-digital converter in the correction mode, and a period of the NRZ signal may be different from a product of a sampling period of the time-interleaved analog-to-digital converter and a number of the plurality of analog-to-digital converters included in the time-interleaved analog-to-digital converter.

An analog-to-digital conversion device is provided that includes a front SAR ADC and a plurality of rear SAR ADCs. The front SAR ADC is configured to convert an analog input signal into a group of higher bits of a digital output signal in response to different time periods. Each of the rear SAR ADCs is electrically coupled to the front SAR ADC and is configured to receive the analog input signal and the corresponding group of higher bits in response to the different time periods. The rear SAR ADCs convert the analog input signal into a group of lower bits of the digital output signal corresponding to the time period of the group of higher bits.

Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

The present disclosure relates to communication devices and provides a method and apparatus for calibrating a sampling timing skew between time-interleaved analog to digital converter (ADC) channels, a time-interleaved ADC, an electronic device, and a computer readable medium. The time-interleaved ADC includes multiple ADC channels. The method includes: calculating, for every two adjacent channels, a correlation value between digital signals of two adjacent channels, according to the digital signals output by every two adjacent channels; calculating a timing skew adjustment amount corresponding to a sampling timing skew of each of the channels relative to a reference channel according to the correlation value corresponding to every two adjacent channels, the reference channel being any designated channel among the plurality of channels; and calibrating the sampling timing skew of each of the channels relative to the reference channel according to the timing skew adjustment amount corresponding to each of the channels.

Technologies directed to a receiver circuit with selective time-interleaved analog-to-digital converters (ADCs) are described. The receiver circuit includes a first ADC, a second ADC, and a digital processing circuit coupled to the first ADC and second ADC that operates in a first mode or a second mode. In the first mode the first ADC receives a first signal and generates first samples at a first sampling frequency. The digital processing circuit processes the first samples. In the second mode, the first ADC and the second ADC both receive a second signal and collectively generate second samples at a second sampling frequency that is greater than the first sampling frequency. The digital processing circuit processes the second samples.

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.

The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.